H5TQ4G83CFR-RDC Brand HYNIX Quantity: 16000 Lot number: 18+ Package: FBGA Brand new and original now Shenzhen Xindachuang Technology Co., Ltd. Mr. Ruan 13682328460 QQ960922153

H5TQ4G83CFR-RDC Specifications:

H5TQ4G83CFR-RDC parameters:

The H5TQ4G43AFR-XXC, H5TQ4G83AFR-XXC and H5TQ4G63AFR-XXC are 4Gb

CMOS Double Data Rate III

(DDR3) Synchronous DRAM, ideal for applications requiring mass storage main memory

density and high bandwidth. 4GB DDR3 SDRAM chip provides full synchronous operation

ing and falling edge of the clock edge. while all address and control inputs are latched on the rising edge

On the CK (belonging to the edge of CK), the data, data strobe and write data mask inputs are sampled for two ripper

ing and dropping it to the brink. The datapath is internally pipelined and 8-bit prefetched to achieve very high

bandwidth.

Equipment Features and Ordering Information

Features:? VDD = VDDQ = 1.5V +/- 0.075V

? Fully differential clock input (CK, CK) operation

? 8banks ? Average update cycle (temperature upper limit 0oC ~ 95oC)

? Differential Data Strobe (DQS, DQS)

- 7.8µs 0oC ~ 85oC- 3.9µs 85oC ~ 95oC

? On-chip DLL aligns DQ, DQS and DQS with CK transitions

?Transition? JEDEC standard 78ball FBGA (X4/X8), 96ball FBGA (X16

? DM masks the rising and falling edges of written data

??Select EMRS driver

data strobe edge

?Dynamic on-chip termination support

?All address and control input data other than data

?Asynchronous reset pin support

Rising edge clock for strobe and data mask latches

? ZQ calibration support ? Programmable CAS delays 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported

? Programmable Additional Latency is 0, CL-1 and CL-2 are supported ? Programmable CAS Write Latency (CWL) = 5, 6, 7 8, 9,

10

? Programmable burst length 4/8 in both cannibalize sequential and interleaved modes ? BL on-the-fly switch

?? TDQS (terminated data strobe) support (x8 only)

?Write Levelization support? 8-bit prefetch? This product is RoHS compliant.