Features

1536 -bit disposable programming (OTP) EPROM, used to store user programming data

Factory programming No.

single-line interface, reduce circuit board wiring

synchronous communication reduces host interrupt overhead

6KV IEC 61000-4-4- 2 ESD compliance on the data pin

No need for backup power supply

provides 3 stitches SOT-23 and To-92 packaging

Application

Security encoding

Inventory tracking

Product revision and maintenance

battery pack group Identification

Description

BQ2026 is a 1.5K serial EPROM, including the only 48 -bit identifier, 8 -bit code and 64 -bit status register of factory programming.

bq2026 SDQ #8482; The interface only needs to connect and one grounding loop. The SDQ pin is also the only power of BQ2026.

Small surface paste packaging options saves print circuit board space, and low cost makes it an ideal choice for battery packs configuration parameters, record maintenance, asset tracking, product revision status, and access code security.

Equipment information

(1), please refer to the software package appendix at the end of the data table at the end of the data table.

block diagram

Overview

Fragrant diagram shows the main control and storage part of BQ2026 Relationship. BQ2026 has three main data components: 64 -bit factories programming ROM, including 8 -bit code, 48 -bit identifiers and 8 -bit CRC values, 1536 -bit EPROM and EPROM status bytes. The power supply of the reading and writing operation comes from the SDQ pin. Internal capacitors store energy when the signal line is high, and releases the energy at the low time of the SDQ pin until the pin returns the high level to supplement the charge on the capacitor.

Function box diagram

Function description

EPROM

Table 1 is the memory mapping of the 1536 -bit EPROM segment of BQ2026 , Configure 6 pages, 32 bytes per page. 1 byte RAM buffer isAdditional registers used during memory programming. First write the data into the RAM buffer, and then verify the correct reception of data by reading 16 -bit CRC from BQ2026. If the content of the buffer is correct, a programming pulse is issued and a 1 -byte data segment is written into the selected address selected in the memory. This process ensures data integrity during memory programming. For detailed information about the 1536 -bit EPROM part of reading and programming BQ2026, please refer to the memory and status function command of this data table.

EPROM status memory

In addition to the programmatic information with 8 bytes with 8 bytes, the first 7 bytes are available for users to use , Includes in EPROM status memory. Status memory can be accessed through separate commands. The status bytes are EPROM, which are read or programmed to indicate various situations to inquire about BQ2026 software. Customers can use these universal bytes to store various information.

Error check

Through the 16 -bit CRC value sent by BQ2026 to achieve an error check. If the two CRC values match, there is no error transmission. For details, see the CRC generation part.

Equipment function mode

Custom BQ2026

64 -bit ID identifies each BQ2026 device. The 48 -bit serial number is the only one, programming by Texas Instrument Company. The default 8 -bit series code is 09h; however, you can retain different values according to a single customer. For more information, please contact your Texas Instrument Sales Representative.

The bus terminal

Since the drive output of BQ2026 is a leakage, N-channel MOSFET, the host must provide an external pull of the source current or 5-k as shown in Figure 1 Show of typical application circuits.

Serial communication

The host reads, programmed or checks the state of BQ2026 through the layered command structure of the SDQ interface. Figure 2 shows that the host must first emit a ROM command to read or modify the EPROM memory or state.

Initialization

Initialization includes two pulses, reset pulses and existence pulse. The host generates a reset pulse, and the BQ2026 has a pulse response. The host resets the BQ2026 by the low level of the data bus at least 480 μs. For more details, see the reset and the pulse part.

ROM command

Reading ROM

Read ROM command sequence is the fastest sequence that allows the host to read 8 -digit code and 48 -bit identification number.Start reading the ROM sequence from the reset pulse of at least 480 μs from the host. BQ2026 uses a pulse response. Next, the host continued to send the Read ROM command 33h, and then read the ROM and CRC bytes of reading (see writing and reading parts) during the data frame.

matching ROM

When the known series code and identification number, the host uses the Match ROM command 55h to select a specific SDQ device. The host issues the Match ROM command, and the series code, ROM number, and CRC byte. Select the device that matches the 64 -bit ROM sequence, and can be used to perform subsequent memory and status functional commands.

Skip ROM

This skip cch command CCH allows the host to access memory and status functions without issuing a 64 -bit ROM code sequence. The SKIP ROM command is a memory or state function command behind.

Memory and status function commands

Four memory and status function commands allow read and modify 1536 -bit EPROM data memory or 7 -byte EPROM state memory. Essence There is a read memory and field CRC command, plus writing memory, reading status, and writing status command. BQ2026 only responds to the memory and status functional command after selecting the device through the ROM command.

Reading memory and field CRC

In order to read the memory, the ROM command follows the Read Memory command F0H, followed by the low -byte of the address, and then the address high byte.

Then, the host issued a read time clearance and received data from BQ2026. From the initial address, it continued to the end of the 1536 -bit data field, or until the reset pulse was issued. If the read occurs at the end of the memory space, the host can send out 16 additional reading time gaps, and the BQ2026 responds to 16 -bit CRC of all data bytes read from the initial bytes of the memory to the last byte. After the host receives the CRC, before the reset pulse is issued, any subsequent reading time slot will be displayed as logic 1s. No 16 -bit CRC can be available before reaching the end of the memory pulse.

Read status

Reading status command is used to read data from the EPROM status data field. After the ROM command is issued, the host emits the Read Status command AAH, then the address is low byte, and then the address is high byte.

Note

The 16 -bit CRC of the command byte and address byte by byte by byte by byte by the address byte by byte by the byte by byte by the byte by bytes, it is calculated by BQ2026 and reads it by the host to confirmReceive the correct commands and start addresses.

If the CRC read is incorrect, the reset pulse must be issued, and the entire sequence must be repeated. If the CRC received by the host is correct, the host sends a reading slot and receives the data from the BQ2026. Starting from the address provided, it continues to the end of the EPROM status data field. At this time, the host received a 16 -bit CRC, which was transferred from the beginning to the last byte to the last byte to transfer to the CRC generator.

The reason why this feature is provided is because the EPROM status information may change over time, so that the data cannot be programmed and includes the always effectively accompanied by CRC. Therefore, the Read Status command provides 16 -bit CRCs stored in the current data based on the EPROM state data field.

After reading 16 -bit CRC, the host received logic 1 from BQ2026 until the reset pulse was issued. Reading status command sequence can end at any point by sending a reset pulse.

Write into the memory

Write into the memory command for programming 1536 -bit EPROM memory fields. The 1536 -bit memory field is programmed by 1 byte. Data first write a 1 -byte RAM buffer. When a programming command is issued, the content of the RAM buffer is ""and"" operational ""with the content of the EPROM memory field.

FIG. 9 demonstrates the event sequence of EPROM memory field programming. After the ROM command is issued, the host issues a memory command 0fh, followed by the low byte of the starting address, and then the high byte. The host sends 1 byte of data to BQ2026.

Calculated and transmitted 16 -bit CRC according to the command, address and data. If the CRC is consistent with the CRC calculated by the host, the host's programming voltage is at least 480 μs or TEPROG.

If the CRC reads the CRC read at any time during the memory process, the reset pulse must be issued, and the entire sequence must be repeated.

Write the data memory command sequence can be terminated at any point by issuing a reset pulse, except for the program pulse cycle tprog.

Note

BQ2026 response data from the selected EPROM address, first send the lowest effective position. This response should be checked to verify the programming bytes. If the programming bytes are incorrect, the host must reset the part and start writing the sequence.

For these two situations, the decision of continuing programming is completely determined by the host, because BQ2026 cannot determine whether the 16 -bit CRC calculated by the host is consistent with the 16 -bit CRC calculated by BQ2026.

Before programming, 1536 -bitThe bit in the EPROM data field is displayed as logic 1.

Writing status

The writing state command is used to program the EPROM status data field after selecting BQ2026 through the ROM command.

The flow chart in FIG. 9 shows that the host emits the Write Status command 55h, then the address is low byte, then the address is high byte, and finally the data by.

Note that

The bytes of the address and data are first transmitted through LSB. The 16 -bit CRC of the command byte, the address byte and the data byte is calculated by BQ2026 and read it back by the host to confirm the receiving the correct commands, starting address and data bytes.

If the CRC read is incorrect, the reset pulse must be issued, and the entire sequence must be repeated. If the CRC received by the host is correct, the programming voltage VPP is applied to the SDQ tube foot, and the duration is TPROG. Before programming, the first 7 bytes of the EPROM status data field are displayed as logic 1. For each bit of logic 0 in the data bytes provided by the host, after the byte position is applied to the programming pulse, the corresponding bit programming in the byte of the selected by the EPROM status data field is logic 0.

After the application programming pulse and the data cable returned to the VPU, the host issued eight read time gaps to verify whether the appropriate position had been programmed. BQ2026 responds to data from the selected EPROM status address, and first sends the minimum effective position. This response should be checked to verify the programming bytes. If the programming bytes are incorrect, the host must reset the device and start writing the sequence. If the BQ2026 EPROM data byte programming is successful, BQ2026 will automatically increase its address counter to select the next byte in the state memory data field. The minimum effective bytes of the new two -byte address are also loaded into the 16 -bit CRC generator as the starting value. The host uses eight writing time slots to send the next byte of data.

When BQ2026 received this byte data to the RAM buffer, it also transferred the data to the CRC generator. The generator had pre -installed the current address LSB, and the result was the new data byte byte And 16 -bit CRC of the new address. After providing data bytes, the host reads the 16 -bit CRC from BQ2026, 8 of which reads the time clearance to confirm the correct increasing address and the data byte is correctly accepted. If the CRC is incorrect, the reset pulse must be emitted and the writing state command sequence must be restarted. If the CRC is correct, the host emits a programming pulse and programming the bytes selected in the memory.

Note

The initial writing of the status command to generate a 16 -bit CRC value. This value is the result of the command byte by byte to the CRC generator. Then there are two addresses. byte,Finally, the data byte. Since the BQ2026 automatically increasing its address counter, the subsequent writing of the 16 -bit CRC in the writing state command is loaded (instead of shifting) the LSB of the new (incremental) address to the CRC generator, and then the new in the new The result of the shift in the data byte.

For these two situations, the decision of continuing to program the EPROM status register is completely determined by the host, because BQ2026 cannot determine whether the 16 -bit CRC calculated by the host is consistent with the 16 -bit CRC calculated by BQ2026. If the incorrect CRC is ignored and the host applies the program pulse, incorrect programming may occur in BQ2026. It should also be noted that BQ2026 always increases its internal address counter after receiving eight reading time slots used to confirm the selected EPROM byte programming. The continued decision is completely determined by the host. Therefore, if the EPROM data bytes do not match the data bytes provided, but the host continues to execute the Write Status command, then incorrect programming may appear in BQ2026. The writing state command sequence can end at any point by sending a reset pulse.

SDQ signal Read the starting frame of the position. Figure 10 shows the initialization time, and Figure 11 and Figure 12 show that the host starts each bit by starting the TWSTRB/TRSTRB driver low data bus. After the bit starts, the host continues to control the bus during the writing period, or the BQ2026 responds during the reading period.

Rebate and Pulse

If the data bus is low by more than 120 μs, BQ2026 can be reset. Figure 10 shows that if the data bus is driven by more than 480 μs, the BQ2026 will reset and indicate that it is ready through response to the existence of pulse.

Writing

In the writing position diagram in FIG. Enter 0, or release the data bus to write 1.

Reading

FIG. 12 Display the host's transmission of the starting bit by the TRSTRB section of the position. Then, the BQ2026 transmits reading 0 by the low level of the data bus, or releases the data bus to transmit reading 1.

Program pulse

FIG. 13 shows the timing of the program pulse.

idle

If the bus is high, the bus is idle. The bus transaction can be counted by concessionIt is hung according to the busy state. Bullet transactions can be recovered from idle at any time.

CRC generation

BQ2026 stored an 8 -bit CRC in the highest effective bytes of 64 -bit ROM. The bus host calculates the CRC value from the top 56 -bit of the 64 -bit ROM and compares it with the value stored in BQ2026 to determine whether the bus host receives an eroded ROM data. The equivalent multi -itit function of the CRC is shown in Figure 14.

In some cases, the BQ2026 also uses the multi -format function shown in Figure 15 to generate 16 -bit CRC value and provide the value to the bus host to verify the command, address and data byte transmission from the bus host from the bus host To BQ2026. BQ2026 Calculates 16 -bit CRC for the command, address and data bytes received by the storage and writing state command, and then output the value to the bus host. The bus host confirms the correct transmission. Similarly, the BQ2026 calculates 16 -bit CRCs that read the command and address byte by the statement from the bus host, as well as the read status command to confirm that these bytes have been correctly accepted.

In each case, if CRC is used for data transmission verification, the bus host must use the polynomial function in Figure 14 or Figure 15 to calculate the CRC value, and the calculation value and the 64 -bit ROM part of BQ2026 The stored 8 -bit CRC value (read for ROM) or 16 -bit CRC values calculated in BQ2026. The comparison of the CRC value and the decision of continuing operations are completely determined by the bus host. If the value of the CRC that is stored in BQ2026 or BQ2026 does not match the value generated by the bus host, any circuit on the BQ2026 will not prevent the command sequence from continuing. Correct use of CRC can make the communication channels highly complete.