Features

Suitable for car applications

18 channel gamma correction

Output

10 -bit resolution

rail transfers

Low power current: 900 μA/CH

123] power supply voltage: 7 v to 18 v

Digital power supply: 2.0 V to 5.5 v

double -line interface: 3.4 MHz High -speed Mode

Provide demonstration boards and software

Application

Replace resistive gamma solutions

#8226; TFT-LCD Reference Driver

Dynamic gamma control

Instructions

buf20800-Q1

is a programmableable available programmable The benchmark voltage generator is used for gamma correction in the TFT-LCD panel. It provides 18 programmable output for gamma correction, two channels for VCOM adjustment, and the resolution of each channel is 10 bits. This programmable replaces the process of changing the resistance value of traditional time to optimize various gamma voltages, and allows designers to quickly determine the correct gamma voltage of the panel. The required changes can also be easily implemented without changing the hardware.

BUF20800-Q1 uses TI's latest small geometric simulation CMOS process, which makes it a very competitive choice for comprehensive production, not just evaluation.

Each output is programmed through the two -line interface of industrial standards. Unlike the existing programmable buffer, the BUF20800-Q1 provides a high-speed mode that allows the clock speed to be as high as 3.4 MM.

For the lower number of channels, please contact your local sales or marketing representatives.

BUF20800-Q1 offers #8482; wrap in HTSSOP-38 power board. The specified temperature range is 40 ° C to+105 ° C.

Related Products

Typical features

TA 25 ° C, vs 18 v, vsd 5V, VREFH 17V, VREFH 17V, VREFL 1V, RL 1.5K ground, CL 200pf, unless there is another instructions.

Application information

BUF20800-Q1 programmable voltage benchmark allows fast and easily adjust 18 programmable reference outputs and two channels for VCOM adjustment. Each channel has 10 resolution of 10-bit resolution Rate. It provides a very simple, efficient gamma reference voltage and VCOM voltage adjustment. BUF20800-Q1 is programmed by high-speed standard dual-line interface. BUF20800-Q1 provides a dual register structure for each DAC channel to simplify the implementation of dynamic gamma control. This structure allows all channels to be updated quickly at the same time.

Cushioner 1 9 can swing within the 200mv range of the positive electrode power supply rail, and swing within the range of 0.6V of the negative electrode power supply track. The buffer 10-18 can swing to the 0.8V range of the positive power supply rail and the 200mv range of the negative electrode power supply rail.

BUF20800-Q1 can use 7V to 18V analog power supply voltage and 2V to 5.5V digital power supply. Digital power supplies must be used or at the same time before or at the same time to avoid excessive current and power consumption; if you only connect to the simulation power supply for a long time, the device may be damaged. Figure 7 shows the regular requirements of power supply.

FIG. 8 shows the BUF20800-Q1 in the typical configuration. In this configuration, the BUF20800-Q1 device address is 74h. Once the data is received in the corresponding register (LD 0), the output of each digital modular converter (DAC) is updated immediately.

For the maximum dynamic range, set VREFH vs 0.2 V and vREFL GND+0.2 V.

Overview of the dual-line bus

BUF20800-Q1 communication through industrial standard dual-line interfaces to receive data from the mode. This standard uses the two -line open -road leakage interface to support multiple devices on a single bus. The bus is only driven to low logic. The equipment that initiates communication is called the main device, and the device controlled by the main device is from the device. The host generates serial clock on the clock signal line (SCL), controls the bus access, and generates start and stop conditions.

In order to address specific devices, when the SCL is at high electricity, the host starts the startup condition by pulling the data signal line (SDA) from high logic levels to low -logo levels. All the machines on the bus are shifted from the address byte by bytes, and the last one said whether it is necessary to read the operation or write operations. During the ninth clock pulse, the sub -addressing machine responded to the host by generating a response and lowering the SDA.

Then start the data transmission, send 8 -bit data, and then send a confirmation bit. During the data transmission process, when the SCL is high, the SDA must be stable. When SCL is high, any change of SDA will be explained as startup or stop conditions.

Once all data is transmitted, the main device will generate a stop condition. When SCL is high, SDA is pulled from low to high.

BUF20800-Q1 can only be used as a device; therefore, it never drives SCL. SCL is just the input of BUF20800-Q1. Table 1 and 2 summarize the address and command code of BUF20800-Q1, respectively.

The address of the buf BUF20800-Q1

The address of the buf20800-Q1 is 111010x, where X is the state of the A0 pin. When the A0 pin is low, the device will be confirmed on the address 74h (1110100). If the A0 pin is high, the device will be confirmed on the address 75h (1110101).

Other valid addresses can be implemented by simple mask changes. Please contact your TI representative to obtain information.

(1), the RC combination optional.

(2), GNDA and GNDD must be connected together.

(3), it is not recommended to connect the capacitor to this node.

Data rate

The dual -line bus runs with one of the three speed modes:

standard: allow clock frequency to reach 100kHz;

Quick: The clock frequency is as high as 400kHz; and

high -speed mode (also known as HS mode): The clock frequency is as high as 3.4MHz.

BUF20800-Q1 is completely compatible with all three modes. Under standards or fast mode, the use of equipment does not require special operations, but the high -speed mode must be activated. To activate the high -speed mode, send a special address byte 00001xxx after the start -up condition, SCL 400kHz; XXX is the only bit of the host of HS, which can be any value. This byte is called HS main code. (Please note that this is different from the normal address bytes, and the low position does not indicate the reading/writing status.) No matter the value of the last three digits, the BUF20800-Q1 will respond to a high-speed command. BUF20800-Q1 will not confirm this byte; the communication protocol is prohibited to confirm the HS main code. After receiving the main code, the BUF20800-Q1 will open its HS mode filter and communicate at a frequency of up to 3.4MHz. By generating uninterrupted repetitions, you can start additional high -speed transmission without sending HS mode bytes. BUF20800-Q1 will exit the HS mode under the next stop condition.

General call reset and power power

BUF20800-Q1 response general call resetting, that is, 00H (0000 0 0000), followed by data byte 06h (0000 0110). BUF20800-Q1 confirms these two bytes. After receiving the general call resetting, the BUF20800-Q1 will perform a complete internal resetting, as if it has been powered off and then turned on. It always confirms the general call address bytes of 00H (0000 0000), but it is not confirmed that any general call data bytes other than 06H (0000 0110) are not confirmed.

BUF20800-Q1 automatically executes reset after power generation. As a reset, all outputs are set to (VREFH VREFL)/2. Other reset value can be used as a custom modification. For details, please contact your TI representative.

After sending the device address, if the valid DAC address is sent, and the bit D7 to D5 is set to ""100"