Double power frequency (2 · FL) ripples that appeared on CFF are triangular, with peak-peak amplitude, as follows:

Among the FL is where FL is Line frequency. Three harmonic distortion related to this three -time harmonic distortion related to the amplitude of 2 · FL component amplitude is:

Figure 36 shows a chart, which can help choose the maximum expectations based on maximum expectations Three harmonic distortion. Always connect RFF and CFF to if the pin is kept floating or directly connected, the IC will not be able to work normally.

The dynamic limit of the voltage feedback input is 0.5V (see Figure 35), if the voltage on the VFF pin is less than 0.5V. This helps to prevent the voltage of the line below the minimum specified value (power -off condition).

THD optimizer circuit

L6563 /A has a special circuit that can reduce the input current near the zero cross point of the zero cross point of the routine of the dead corner ( Cross deformation). In this way, the THD (total harmonic distortion) of the current is quite reduced. One of the main reasons for this distortion is that the system cannot effectively pass the energy when the instantaneous wire voltage is very low. This effect is enlarged by the high -frequency filter capacitor behind the bridge rectifier, and it retains some residuals that cause the backbone voltage of the bridge rectifier diode to temporarily stop. In order to overcome this problem, the device forced the PFC to pre -process more energy to deal with more energy. The voltage of the line was over zero, compared with the instruction of the control loop. This will minimize the time interval of insufficient energy transmission and rely on the bridge after the high -frequency filter capacitor is carried. Figure 37 shows the internal box diagram of the THD optimizer circuit.

In essence, the circuit passengers increase the connection time of the power switch. Offset. When the transient line voltage increases, the offset decreases, so when the line voltage moves to the top of the sine curve, it can be ignored. In addition, the offset is the voltage modulation on the VFF pin (see p. 18.3), so that the offset at the low line is very small. And the greater the offset of the high -voltage line with a difference in energy transmission. The effect of the circuit is shown in Figure 38, and the key waveform of the standard TM compares the PFC controller with the chip. In order to maximize the use of THD to optimize circuits, high -frequency filter capacitors should be reduced as much as possible after rectification bridges, compatible with the needs of EMI filtering. In a large, the capacitance itself introduces the conduction dead end of AC input current-even through the PFC pre-regulator to realize the ideal energy transfer, it also reduces the efficiency optimizer circuit.

Tracking enhancement function

In some applications,The output voltage of the PFC pre -regulator may be favorable so that it can track the RMS input voltage instead of the IN conventional supercharged pre -regulator. This is usually called tracking promotion or follower promotion method. With this integrated circuit, the function and ground can be implemented by connecting resistors (RT) between TBO pins. The DC level of the TBO pin is equivalent to the peak of the multi -pin voltage and the validity voltage of the power supply. The resistor defines a current, which is equal to V (TBO)/RT, that is, the internal 1: 1 mirror and enter the depression amplifier from the wrong pins (pins 1). In this way, when the power supply voltage increases, the voltage on the TBO pin will increase the current and connect to the TBO and ground. In this way, the INV tube foot will generate a large current, and the output voltage of the PFC pre -regulator will be forced to rise. Obviously, the output voltage will move in the direction of the reverse input voltage. In order to avoid rising output voltage, if the power supply voltage exceeds the maximum value specified value, the voltage at the TBO pin is shown to 3V. By the correct selection of the bias of the ingel-can be set to the maximum input voltage tracking of the input to the output, the output voltage is kept constant. If you do not use this function, leave your pin: The device will adjust a fixed output voltage.

Starting from the following data:

vin1 minimum input RMS voltage;

vin2 maximum input RMS voltage;

vo1 adjust the output voltage @Vin vin1;

vo2 adjustment output voltage@vin vin2;

vox the absolute maximum limit of the adjustment output voltage;

#8710; vo OVP threshold,

Use the following design program to set the output voltage as the required value: determine the input RMS voltage of VOX vINCLAMP:

Vinx lt; vinclamp. This will lead to the output voltage range below VOX (if vinx vinclamp, it is equal to VOX) to determine the multiple pins (pin 3) bias division ratio:

and check at the minimum minimum at the minimum Under the power supply voltage VIN1, the peak voltage on the pin 3 is greater than 0.65 volts. Determine the R1, the upper resistance of the output division:

Calculate the lower resistor R2 and adjust the resistor RT:

] Calculate the lower resistor of the output pressure device R2 and check the maximum current provided by the TBO pin (pin 6) does not exceed the maximum specified value (0.25ma): adjust the resistor RT:

[ 123]

In the worksheet in mathcad #174;The calculation is shown in Figure 40. FIG. 41 shows the internal frame diagram function of tracking enhancement.

Design data

vin1: 88V voltage: 200V

vin2: 264v Voltage: 385V

Voltage 400V

] #8710; VO; 40V

] The saturation detection of inductors (only L6563)

The hard saturation of the boost electrocarchers may be the fatal event of the PFC pre-adjuster. ), Induction of delay current during ocean current may reach abnormal high values. The voltage drop is reduced by an abnormal current caused by abnormal currents on the sensing resistance, so MOSFET can work in the active area and consume a lot of power, which will cause disaster failure after several switching cycles. However, in some applications, such as the AC-DC adapter, in order to save energy, even a well-designed boost electromotor can be turned off. When the PFC stage is re-started due to a large load, the PFC level is restarted due to a large load. Occasionally, mild saturation needs occur. This happens when re -activation occurs in an unfavorable line voltage phase, so the output voltage may be significantly lower than the rectifier peak voltage. Therefore, the wave current of the voltage sensor comes from the bridge rectifier, the current is added to the switch, and there is almost no or no voltage used for demagical. In order to handle saturated inductors, L6563 is at the current quotation (CS, pin 4). If the voltage is limited normally, the IC is stopped and the IC is locked in 1.1V, exceeding 1.7V. It can also be assertive as a high -level PWM U 闩 lock pin. In this way, the entire system will stop and enable it can only be restarted after recycling the input power, that is, when the VCC voltage PWM controller of the L6563 will be lower than the respective UVLO threshold. System security has increased significantly. To better adapt to the application of a saturated voltage sensor to a certain extent, tolerance is that L6563A does not support this protection function.

Power Management/Internal Affairs Management Function

One feature of the integrated circuit is that it is easy Circuit required for the transformer work. The function of the implementation of the interior management circuit ensures that the transients such as power -powered or power -off or any power -level failure are properly handled. This device provides some pins to achieve this. As mentioned earlier, the integrated circuit of a communication line-level DC-DC converter and the PWM controller are the pulse width modulation locks. When the power factor is working properly, it often opens. High loss of control to the output voltage (due to controlDetaire failure) or inductance saturation, the purpose is to lock the PWM controller converter (Section 6.2: Feedback Fail Protection (FFP) on page 18 to learn more details). The second communication line can be included in the PFC_OK pin (more detailed information, see page 18.2). Usually this line is used to allow the PWM controller to lightly loaded the PTC-DC converter to minimize the air load input consumption as much as possible. If there is a problem with the remaining chip, the power supply can be reduced. The interface circuit is as shown in Figure 43, of which L6563/A and L5991 PWM controller work have a good use of the function and can be used. Needless to say, this operation assumes that the Lianlian DC-DC transform device level is the main level, and the PFC level is first started as a level or in other words. The DC-DC stage is first started.

Article 3 The communication line is PWM_STOP pin (pin 9), which is with positioning (sales 10). The role of the PWM U STOP script is to inhibit the PFC-level and class DC-DC converter. The pins are the opening of the road, and it is often turned on. It must be pointed out that this function is the main level in the PFC level, and the class DC-DC converter is from the level. Essence This function is very flexible and can be used in different ways. When containing auxiliary converters and main converters (such as a silver box or high -end LCD TV of desktop computers), when the auxiliary variables also power the controller of the main stream, the pin operation can be used to start and stop the main variant stream Instrument. In the simplest case, the stopp up pins of the pulse width of the controller can be connected to any wrong output amplifier (Figure 44A) or if the chip is equipped with it, it can be connected to its soft start ( Figure 44B). The use of this soft starting pin allows designers to delay the launch of the DC-DC stage about the PFC stage, which is often needed. Basic assumptions to make it work normally, the UVLO threshold of the PWM controller is high than L6563/A.

If it is not, or it is impossible to achieve sufficiently long start latency (because this will prevent the DC-DC level from correctly start), or simply speaking, the PWM controller is due to the due to the PWM controller due to Without a soft start, the layout of FIG. 45 allows the voltage generated by the PFC stage to reach the preset value when the DC-DC converter starts. Technology depends on the UVLO threshold of the PWM controller.

Another possible use operation and pulse width modulation stop pins (similarly, in the system, the PFC stage is the owner) is the protection of fire, thanks to the lag. The power -off protection is basically a non -lock -locking device. When the power supply voltage is too low, it must be activated. This situation may causeDue to the large value current, the power supply part is too hot.Brown cans also cause the PFC pre -regulator to open the loop, which may cause danger to PFC if the input voltage suddenly restores to the rated value.Another problem is the false restart that may occur during the converter's power supply process.For these reasons, it is usually best to turn off the unit during power outages.

As shown in Figure 46, the IC shutdown on the left during power off is universal. The right on the right can be used on the bias level and the specified time and the level of browfSomewhat deductive time.In Table 6, you can find all the above working conditions to lead to the equipment stop work