The ISL6118 is a dual channel, fully independent overcurrent protection (overclocking) fault protection IC from +2.5 V to +5.5 V ambient. The device features internal current monitoring, accurate current limit, integrated power switch and protection by a current limited delay latching system. The current sense and limit circuits of the ISL6118 set the rated current limit to 0.6A, which is well suited for 3.3 auxiliary ACPI applications. Is the ideal ISL6118 companion chip to the HIP1011D and HIP1011E dual PCI hot-plug controllers. Together with these full ISL6118 four legacy PCI control voltages (± 12V, +3.3 V, +5 V for power) and 3.3V auxiliary, respectively, for the two control power PCI slots compliant with the PCI bus power management interface Specification 1.1 Revision. Designed to be located on the motherboard in conjunction with the HIP1011D, the OC provides the ISL6118 fault notification, precise current limiting and consistent timing latching thus isolating and protecting the voltage bus OC present in all PCI bus power or short circuit events Status as defined by the PCI specification. The 12 ms time latching is independent of the adjacent switch electrical or thermal conditions and the OC response time is negatively correlated with the OC size. Each ISL6118 integrates a second package of 80mΩ N-channel MOSFET power switches in a single 8-pin SOIC for power control. The output of each switch is provided by a constant current source with a controlled ramp register voltage. This provides a soft-start turn-on to eliminate the inrush current caused by the bus voltage sag while charging the load capacitance. Makes the input and independent per-channel fault reporting output compatible with 3V and 5V logic, allowing external control and monitoring. The ISL6118 undervoltage (UV) feature prevents shutdown unless the correct state and output enable VIN > 2.5V is present. Turn on the ISL6118 initially
Prevents blanking of fault signal fault reports. The rising and falling edge output current limits the voltage rise so that both the inrush current and the rate of change of the voltage are limited and independent of the load. This will reduce surges due to supply droop and eliminate the need for external EMI filters. During operation, once the OC condition is detected, the corresponding output current is limited to 12 msec and is allowed to pass under transient conditions. If there is still current limit after the current limit period has elapsed, the output latches are turned off and a fault is reported corresponding to pull the fault low. The fault signal is latched until the reset low enable signal is pulled high, at which point the fault signal will clear.