Features

can be configured as a linear or PWM mode VCM current generation

VCM efficient PWM current control

Advanced ringtone compensation

Integrate 10 -bit D/A converter for VCM current control

Protection

- Opening and short -circuit detection [ 123]

-IOU locking (UVLO)

-The internal current limit of the heat shutdown

--VCM drive

-4 kV ESD-HBM

I2C interface

improve the setting time of PWM to linear mode. Compared with DRV201, EMC performance is improved compared to DRV201. 123]

Improve the stability time of PWM to linear mode. Compared with DRV201

Compared with DRV201, EMC performance has improved

Working work Temperature range: -40OC to 85OC

6 ball WCSP components, 0.4 mm

Maximum size: 0.806 mm × 1.49 mm

the largest packaging height: 0.3 mm

Application

Mobile phone autofocus

digital camera autofocus

iris and exposure control

Security camera

network and PC camera

Explanation

DRV201A

is an advanced audio rotor driver for autofocus of the camera. It has an integrated D/A converter to set VCM current. VCM current is controlled by a fixed frequency PWM controller or linear mode drive. The current can be selected through the I2C register. DRV201A has an integrated sensing resistance for current adjustment, and the current can be controlled through I2C.

When changing the current in VCM, the camera bell compensates through the high -end bell compensation function. The compensation of the bells greatly reduces the time required for autofocus. This device also has a short -circuit and opening protection function of VCM.

Equipment information

(1) For all software packages available, please refer to the appointment appendix at the end of the data table.

Simplified schematic diagram

Typical features

Detailed description

Overview [overview [overview

Overview [overview

Overview [overview

Overview [overview 123]

DRV201A is used for high -performance autofocus in the camera module. It is used to control the current in the audio motor (VCM). The current in VCM generates a magnetic field, forcing the lens group to move on the spring. VCM current and lens positions can be controlled through the I2C interface, and automatic focusing function can be achieved.

DRV201A has a higher performance level than DRV201 in two aspects. First, there is no resonance in PWM and linear mode. This allows faster image capture after being focused in PWM mode. Another performance enhancement is in terms of EMC performance. Compared with DRV201, when working in PWM mode, the conversion slows down significantly, resulting in lower conduction and radiation noise.

The device is connected to a video processor or image sensor by supporting a standard I2C interface supporting up to 400kbit/s data rate. Digital interface supports the IO level of 1.8 V to 3.3 V. All pins have a rated value of 4-KV HBM ESD.

When the SCL is low at least 0.5 milliseconds, the device enters the shutdown mode. If the SCL enters the standby mode within 100 μs from low to high, the default register value setting is shown in Figure 5. As long as the VCM U current register is set to the value other than zero, enter the activation mode.

VCM current can be controlled through the I2C interface and VCM U current register. When a bell lens is connected to a damping lens position, a bell shot is changed. Whenever the current value in the VCM U current register changes, internal compensation is made by generating a optimized slope. This makes a fast automatic focus algorithm and a pleasant user experience.

The current in VCM can be generated by linear or PWM. In the linear mode, the high -voltage side PMOS is configured to the current source, and the current is set by the VCM U current control register. In PWM control, VCM is driven by a half -bridge drive. Through PWM control, the VCM current connects to the VCM between VBAT and GND through the high voltage side PMO, and then releases to the free rotation mode through the inductive resistor and low -voltage side NMO. The PWM mode switch frequency can be selected by controlling registers from 0.5 MHz to 4 MHz. You can use the PWM/Lin bit in the mode register to select PWM or linear mode.

Figure Figure

Feature description

vCM drive output stage operation

The current in VCM can be controlled by linear or PWM mode output level. The output stage is enabled in the activation mode. It can be controlled by the VCM U current control register. The output level mode is selected from the mode register position PWM/Lin.

Under the linear mode, the output PMOS is configured as a high -voltage side current source, and the current can be controlled from the VCM U current register.

In PWM control, VCM is driven by a half -bridge drive. Through PWM control, the VCM current connects to the VCM between VBAT and GND through the high voltage side PMO, and then releases to the free rotation mode through the inductive resistor and low -voltage side NMO. The current in the VCM is determined by a 1Ω sensing resistance, which is connected to the input terminal of an error amplifier, and the other input is controlled by 10 digits of the DAC output terminal. The PWM mode switch frequency can be selected by controlling registers from 0.5 MHz to 4 MHz. You can use the PWM/Lin bit in the mode register to select PWM or linear mode.

Ringling compensation

VCM current can be controlled through the I2C interface and VCM U current register. The lens group is connected to a spring. When the current changes, the spring will cause damping bell at the lens position. Whenever the current value in the VCM U current register changes, internal compensation is made by generating a optimized slope. This makes a fast automatic focus algorithm and a pleasant user experience.

Ringling compensation depends on the VCM resonance frequency, which can be controlled from 50 Hz to 150 Hz through VCM frequency registers (07H). Table 1 shows the VCM_ frequency register setting of each resonant frequency of 1-Hz. If there is a more accurate resonance frequency, the control value can be calculated with equations 1.

The design method of ringing compensation is that when using 2/FVCM compensation, it can tolerate the frequency change of ± 30%of the VCM resonance frequency, and for 1/FVCM, it can tolerate the change of ± 10%. Therefore, only VCM statistics are required in production.

Equipment function mode

Operation mode

Close: If the driver detects the DC level of the SCL below 0.63V and continues at least at least at least at least 0.5ms, the driver will enter the shutdown mode. This is the minimum power running mode. As long as the driver keeps low in the SCL, closing the pin will be kept.

Spare items: If the SCL enters the standby mode from low to high from low to high, the driver enters the standby mode and sets the default register value. In this mode, the register can be written through the I2C interface. When the VCM U current register is set to zero, the device will be in the standby mode. If you set the first place to control the register, the device will enter the activity mode to enterMachine status. In this case, all registers will be reset to the default value.

If any failure occurs, enter the standby mode from the activation mode: overheating protection failure (OTPF), VCM short circuit (VCM) or VCM opening (VCMO). When the failure state enters the standby mode, the current register is cleared.

Activation: When the VCM U current control is set to be set to zero through the I2C interface, the device is in the activity mode. In the activity mode, the VCM drive output level is always enabled, resulting in higher power consumption. Before setting the first SW bit in the control register, the SCL lowered 0.5 milliseconds, the VCM U current control settings to zero or any failure occurred, the device maintenance mode: overheating protection failure (OTPF), VCM short circuit (VCMS) (VCMS) Or VCM opening (VCMO). If you enter the activation mode after the failure, the status register will be cleared automatically.

Programming

I2C bus operation

I2C bus is a communication link between the controller and a series of machine terminals. The link uses two line bus consisting of a serial clock signal (SCL) and serial data signal (SDA). The serial clock is from the controller when the serial data cable is two -way, for all the data communication between the controller and the terminal of the machine. Each device has an output of a leaky open road, which is used to transmit data on the serial data cable. A external pull -up resistor must be installed on the serial data cable so that the drain output is raised during the data transmission process.

DRV201A has a data rate and automatic incremental addressing address of up to 400kbit/s from the I2C interface, which meets the I2C standard 3.0.

DRV201A supports four different reading operations and two different writing operations: a single reading from the definition position, a single reading from the current position, the order of reading from the definition position, reading from the definition position, and starting from the definition position. Read from the order of the current position, to a single writing of the definition position, and starting from the definition position. Here are all different reading and writing operations.

Single writing to the specified position

FIG. 6 shows the format of a single writing of the defined register. First, the host issues a startup condition, followed by a 7 -digit I2C address. Next, the host writes a 0 to perform the writing operation. After receiving the answer from the machine, the main device writes 8 -bit registers through the bus. After the second confirmation, DRV201A set the I2C register to a defined value, and the host wrote 8 -bit data values u200bu200bthrough the bus. After receiving the third confirmation, the DRV201A automatically adds an internal I2C register number by one, and the main device issues stop conditions. This operation end the register.

Perform a single reading from the definition position and current location

FIG. 7 shows the format read from a defined position. First, the host issues a startup condition, followed by a 7 -digit I2C address. Next, the host writes a 0 to perform the writing operation. After receiving the answer from the machine, the main device writes 8 -bit registers through the bus. After the second confirmation, the DRV201A set the internal I2C register number to the defined value. Then the host sends out a repeated startup condition and a 7 -digit I2C address, and then an address to perform the reading operation. After receiving the third confirmation, the main device releases the bus to DRV201A. Then DRV201A writes 8 -bit data values u200bu200bfrom the register through the bus. The host confirms that receiving this byte and issuing a stop condition. This operation end the register read.

FIG. 8 shows a single reading from the current position. If the Read command is issued without the first definition of the register number, the DRV201A writes the data in the current register from the device memory.

Sequential reading and writing

Sequential reading and writing allows simple and fast access to the DRV201A register. Figure 9 shows the order of reading from a defined location. If the host does not issue stop conditions after ACK is given, the DRV201A will automatically add the register number and write the data from the next register.

FIG. 10 shows the order of writing. If the host does not issue a stop condition after the host is given, the DRV201A will automatically increase its register, and the host can write the next register.

If you start reading without writing the value of the register first, then DRV201A will write data from the current position. If the host does not issue stop conditions after ACK is given, DRV201A will automatically increase the I2C register and write data. This will continue to the host to issue stop conditions. As shown in Figure 11.

IC device address, startup and stop conditions 2

Data transmission is started by the starting bit of the controller, as shown in Figure 12. When the SDA cable is converted from high to low at the high part of the SCL signal, the start -up condition can be recognized. After receiving the starting bit, the device will receive serial data on the SDA input and check the effective address and control information. SDA data is rising from the DRV201A lock. If the appropriate device address is set for the device, after the DRV201A is locked in the 8th place, it will be ACK by leaving the SDA cable to the lower side. SDA remains at a low level until the next drop of the SCL line.

Data transmission is completed by receiving stop conditions or receiving data words sent to the device. Stop conditions are considered inDuring the high part of the SCL signal, SDA inputs from low to high. All other transitions of the SDA cable must occur in the low part of the SCL signal. Firmation is issued after receiving valid addresses, sub -addresss and data words. Reference Figure 13.

Application and implementation

Note

The information in the following application chapters is not part of the TI component specification. TI does not guarantee its accuracy Or integrity. TI's customers are responsible for determining the applicability of the component. Customers should verify and test their design implementation to confirm the system function.

Application information

DRV201A device is a sound coil motor drive, designed for autofocus of the camera. The device allows high -efficiency PWM current control to VCM, while reducing the ringing of the lens, which significantly shortens the time required for the automatic focus of the lens. The following design is a common application of the DRV201A device.

VCM mechanical ringing frequency

Ringling compensation depends on the VCM resonance frequency, which can be controlled from 50 Hz to 150 Hz through the VCM frequency register (07H). The VCM mechanical ringing frequency of the bell compensation can be selected for formula 3. The formula is given VCM_FREQ [7: 0] register value (decimal system), which should be entered the closest integer.

The default VCM mechanical ringing frequency is 76.4 Hz.

Typical application

Application curve

[ 123]

Power suggestion

DRV201A equipment is designed to work under VBAT from input voltage of 2.5 to 4.8 V. Users must place at least one rated voltage near the VBAT and GND pins of at least 6.3 V 1-UF ceramic side electric container.

Layout

Layout Guide

Should use low ESR ceramic side electric container to winger VBAT pins to GND. 6.3V. Place the capacitor where near the VBAT and GND pins as possible, and connect it with the device GND pins or ground plane.

layout example