The Texas Instruments PCI2250 PCI-to-PCI Bridge provides two high-performance connection paths to the Peripheral Component Interconnect (PCI) bus. Transactions occur between the master on one PCI bus and the target on another PCI bus, and the PCI2250 allows bridged transactions to occur on both buses simultaneously. The bridge supports burst mode transmission to maximize data throughput, independent of the traffic path between the two buses across the bridge. The PCI2250 bridge is compliant with the PCI local bus specification and can be used to overcome the limitation of electrically loading 10 devices per PCI bus and devices, creating a layered bus per PCI expansion slot. "The PCI2250 provides up to four secondary bus masters with two layers of internal arbitration and may implement external secondary PCI bus arbitration. The PCI2250 provides compact PCI (CPCI) hot-plug expansion capability, which makes it an ideal The solution is a multifunctional compact PCI card and hot-swappable compliance adapts to a single function card. The PCI2250 bridge is compliant with the PCI to PCI bridge specification. It can be configured to actively decode or trim the decode on the host interface and provide some additional decode options, making it ideal as a bridge for custom PCI applications. Two expansion windows are included, and the PCI2250 provides serial decoding and parallel port addressing. The PCI2250 is compliant with PCI Power Management Interface Specification revisions 1.0 and 1.1. In addition ,PCI2250 provides PCI CLKRUN bridge support for low power mobile and docking applications.PCI2250 has been designed to lead the industry in energy saving.Utilize advanced CMOS process to achieve low system power consumption while operating at PCI clock rates up to 33 MHz.

Features
The PCI2250 supports the following functions:
• Configurable to support PCI Power Management Interface Specification Revision 1.0 or 1.1 • Compact, PCI-friendly silicon defined by the Compact PCI Hot-Plug Specification • 3.3 V core logic with common PCI interface, compatible with 3.3 V and 5 V PCI Signal Environment • Two 32-bit, 33 MHz PCI buses • Provides up to 4 secondary bus masters for internal two-level arbitration and supports external secondary bus arbitration • Burst pipeline architecture, data transfer maximizes between two Data throughput in one direction • Provides programmable expandable Windows and port decoding options • Independent read and write buffers for each direction • Provides five secondary PCI clock outputs • Predictable latency per PCI local bus specification • Propagated bus lockout • Moderate bus drive for LOW during reset • Provides VGA palette memory and I/O and subtractive decoding options • Advanced sub-micron, low power CMOS technology • Fully compliant with PCI to PCI bridge architecture specification • Packaged in 160-pin QFP (PCM) and 176-pin thin QFP (PGF)