Features

High -efficiency power level (up to 96%), with low RDS (on) MOSFET (TJ 25 ° C is 80 m )

] working power supply voltage up to 50 V (maximum 65 V absolute value)

each device 10 A continuous output current and 24 A peak current

#8226 ; Pywm operating frequency is as high as 500 kHz

Integrated self -protection circuit

Independent power and ground pins of the bridge

Smart gate driver and anti -intersection fork conductivity

] thermal enhancement DKD (36 -pin PSOP3) package

Application

DC and brushless DC motor

Three phases forever forever Magnetic synchronous motor

Robot and touch control system

Pumps

Precision instrument

TEC driver

Instructions

DRV8402

is a high -performance, integrated double -bridge motor driver and advanced protection system. Due to the design of low RDS (ON) and smart door drives, the efficiency of this motor driver can reach 96%, which allows smaller power and radiator to be a good candidate for energy -saving applications. The device needs two power supply, one for GVDD and VDD, the other for PVDD, and the other is up to 50V. The DRV8402 can drive 5A continuous cubes and 12A peak currents, and each bridge has low idle power consumption. It can also be used for continuous currents up to 10A and the peak current of 24A.

DRV8402 can work at a switching frequency of up to 500 kg, while still maintaining accurate control and efficiency. It also has an innovative protection system integrated on the chip, and the protection equipment is exempted from the effects of various fault conditions that may damage the system. These protection measures include short -circuit protection, over -current protection, under pressure protection, and two -level heat protection. DRV8402 has a current -limiting circuit that prevents the device from being stopped during load transient (such as motor startup). Programmable over -current detector allows adjustable current limits and protection levels to meet different motor requirements.

DRV8402 Each semi -bridge has a unique independent power supply and connectionGround pins, which make it possible to provide current measurement through external parallel resistors and support multiple motors with different power supply voltage requirements.

Simplified application diagrams

System frame diagram

Typical features

Operation theory

Power supply

In order to help the system design, in addition to power -level power supply, DRV8402 only requires 12 volt power. The internal voltage regulator provides a suitable voltage level for the number and low -voltage simulation circuit. In addition, all circuits that require floating voltage power supply, for example, high -voltage side grid drives are accommodated by built -in self -random circuits with only a few external capacitors.

In order to provide electrical characteristics, the PWM signaling pathway, including gate -drive and output -level PWM signal, is designed as the same, independent semi -bridge. Therefore, each semi -bridge has an independent gate -drive power supply (GVD_X), guidance pins (BST_X), and power -level power pins (PVDD_X). In addition, an additional pipe foot (VDD) is provided as a power supply for all public circuits. Although it is powered by the same 12-V power supply, it is recommended to use 1–10 resistor to separate the GVDD_X pin from the VDD on the printed circuit board (PCB). Pay special attention to putting all counter -coupled containers as close to its related pins as possible. Generally speaking, the inductance between the power pin and the decoupled capacitor must be avoided.

For the self -lifting circuit of normal work, a small ceramic capacitor must be connected between each self -raising (BST_X) and the power -level output pin (OUT_X). When the power -level output is low, the self -raising capacitor is charged by the internal diode between the capacitors connected to the grid drive power (GVD_X) and the internal diode between the self -lifting pole. When is the power -level output high, the power of the self -raising capacitor is higher than the output potential, so it provides a suitable voltage supply door drive for the high -voltage side. In the application of the PWM switching frequency range of 25 kHz to 500 kHz, it is recommended to use 47 NF ceramic capacitors with a size of 0603 or 0805 as a self -raising power supply. These 47 -nama capacitors ensure sufficient energy storage. Even with the smallest pulse width modulation, the high -side power level field effect transistor can be kept completely turned on during the remaining pulse width modulation cycle. In an application with a switching frequency below 25KHz, the value of self -lifting capacitors may need to be increased.

Pay special attention to power -level power supply; this includes component selection, PCB placement and wiring. As shown in the figure, each semi -bridge has independent power -level power pins (PVDD U X). The optimal electrical performance compliance and system reliability are important to separate each PVDD_X tube foot from the ceramic capacitor, as close to each power pipe foot as much as possible. It is recommended to follow the EVM boardThe PCB layout of DRV8402.

The 12V power supply should come from a low noise, low output impedance voltage regulator. Similarly, suppose 50V power -level power supply has low output impedance and low noise. Due to the convenience of the internal power -power reset circuit, the order of power is not important. In addition, the DRV8402 completely prevents the error power level caused by parasitic grid charging. Therefore, the voltage supply slope (DV/DT) is non -critical within the specified range (see the recommended operating conditions of this data table).

The order of power -off/power off the system

Energy improvement

DRV8402 does not require the order of power. The output of the H bridge is maintained at a high impedance state until the gate -drive power supply voltage (GVDD_X) and VDD voltage are higher than the voltage threshold of the under voltage protection (UVP) voltage (see the electrical characteristics of the data table). Although it is not specially required, it is recommended to keep the reset_ab and reset_cd in a low state when powering the device. This allows internal circuits to charging the external self -raising capacitors by the weakened pull -down (except the semi -bridge mode) of the semi -bridge output.

Power off

DRV8402 does not require the order of power off. As long as the grid drive power supply (GVDD U X) voltage and VDD voltage are higher than the UVP voltage threshold (see the electrical characteristics of the data table), the device will be fully operated. Although there are no special requirements, it is a good approach to keep Reset_AB and Reset_cd low during the power -off period to prevent any unknown state during this conversion.

Error report

The failure and the OTW pin are low -electric open roads. Their function is to send protection mode signals to PWM controller or other system control devices.

Any fault that causes device shutdown to a low change from the fault pins to a signal. Similarly, when the component temperature exceeds 125 ° C, OTW becomes lower (see Table 1).

Whether it is a reset failure or a reset failure, it must be noted that U is a high level failure. In order to report errors correctly, please set the Reset AU AB and Reset U CD during the normal operation.

TI is recommended to use the system microcontroller to monitor the OTW signal and respond to the OTW signal by reducing the load current to prevent the device from further heating and cause the device to overheat (OTSD).

In order to reduce the number of external components, a 3.3V internal pull -up resistance provided in the fault and OTW output end. The level compliance of 5V logic can be obtained by adding external pull -up resistors to 5V (for further specifications, see the electrical characteristics of the data table).

Equipment protection system

DRV8402 contains advanced protection circuits.Over careful design helps system integration and ease of use, as well as permanent faults in protecting equipment due to various failure conditions such as short circuit, over current, overheating, and under pressure. DRV8402 responds to the failure by immediately set the power level to high impedance (Hi-Z) state and assertive the failure of the failure. In the case of overcurrent or overheating, when the fault conditions are eliminated or the voltage of the gate power supply is increased, the device is automatically recovered. In order to obtain as high reliability as possible, recover from over -current shutdown (OCSD) or OTSD failure requires external reset to the device within 1 second after shutdown (see the device reset part of this data table).

Self -lifting capacitors owed pressure protection

When the device runs at a lower switch frequency (for example, the use of 47 NF self -lifting capacitors is less than 20 kHz), the voltage of the self -raising capacitor may not be the can not be the voltage of the capacitor. The high -voltage side grid drive maintains a proper voltage level. In this case, start a self -lifting capacitance under pressure protection circuit (BST_VP) to prevent the potential failure of the high -voltage side MOSFET. When the voltage on the capacitor is lower than the voltage required for safe operation, the DRV8402 will start the self -lifting capacitor charging order (a short -voltage -off high -voltage side effect transistor), until the self -raising capacitor is charged correctly to achieve safe operation. This function can also be activated when the PWM duty ratio is too high (such as higher than 99.5%). Note that if there is no load on the output terminal, the guide capacitor may not be charged.

Because the extra pulse width of the self -raising capacitance is very short, the output current interruption caused by additional charge due to the existence of the output inductance can almost ignore it.

Overcurrent (OC) protects the device with an independent, fast -response current detector, and has a programmable check threshold (OC threshold) on all high and low -side power grades. There are two OC protection settings through mode selection pins: cycle cycle (CBC) flow limit mode and OC atresia (OCL) shutdown mode.

In the CBC flow limit mode, the detector output is monitored by two protection systems. The first protection system controls the power level to prevent the output current from further increased, that is, it executes the CBC flow limit function instead of turning the device prematurely. This characteristic can effectively limit the motivation of motor startup or during the transient process without damaging the device. In the case of short-circuit and grounding of the power supply, the current limiting circuit may not be able to control the current at the appropriate level. The second protection system triggers the atresia shut off, resulting in the power level set to high impedance (Hi-Z) state. Restrictions and overcurrent protection are independent of half -bridge A, B, C, and D, respectively.

In the OCL shutdown mode, the circular current limit and error recovery circuit are disabled, and the over -current situation will cause the device to close immediately. After shutting down, the reset_ab and/or reset_cd must be asserted to resume normal operation after eliminating the current conditions.

In order to increase flexibility, the OC threshold can beUse a single external resistor connected between the OC_ADJ pins and the AGND pins within a limited range for programming. For information about the correlation between programming resistance and OC threshold, see Table 2. It should be noted that the normal -working over -current detector assumes that there is an appropriate inductor at the power -level output terminal (at least 2 μH). Short -circuit protection is not directly provided on the power -level output pins, but only provides after the inductors. If you choose smaller inductors for any reason, it is recommended to use OCL mode settings.

over -temperature protection

DRV8402 has a two -stage temperature protection system. When the device has a temperature of more than 125 ° C (nominal value), the device will Send an activated low alarm signal (OTW); if the device has a temperature of more than 150 ° C (nominal value), the device will enter the hot stack state, resulting in the high impedance (Hi-Z) state of all semi-bridge outputs, the fault, the fault Being assertive is low. In this case, OTSD is locked, and RESET_AB and Reset_cd must be assertive.

UVP and POR circuits of the underwriting (UVP) and the power -on reset (POR)

DRV8402 are fully protected equipment under any power -powered/off -power and power -off. At the time of power, the POR circuit is reset to the current circuit and ensures that when the voltage of the GVDD U X and VDD power supply reaches 9.8 V (typical values), all circuits can be fully working. Although GVDD U X and VDD are monitored independently, any VDD or GVDD_X pins below the UVP threshold drop will cause all semi-bridge output to be immediately set to high impedance (Hi-Z) state. Essence When all the power supply voltage on the capacitor is higher than the UVP threshold, the device will automatically resume operation.

Equipment reset

provides two reset pins for independent control of semi -bridge A/B and C/D. When the RESET U AB was asserted to be low, all four power-level FETs in the Bridge A and B were forced into high impedance (Hi-Z) state. Similarly, asserting that the low reset is forcing all the four power grades in the semi -bridge C and D to enter the high impedance state.

In the configuration of the full bridge and parallel bridge, in order to adapt to the self -lifting charging before switching, the reset input is set to low to make the drop -down capacity of the semi -bridge output weak. In the half -bridge configuration, the weak drop is not enabled. Therefore, it is recommended to provide a low pulse at the PWM input terminal at the PWM input terminal at a high electricity.

An assertion that the reset input low will delete any fault information to send a signal on the failure output, that is, the fault is forced to high level.

The transition allowed device of any one on the subtraction input is resumed after the current fails.

Different mode operations

DRV8402 supports three different modes of operations:

1. Full bridge (FB) mode

2. Parallel bridge (PFB) mode

3, half -bridge (HB ) Mode

In the full bridge and half -bridge mode, PWM 峎 A controls the half -bridge A, PWM 峎 B to control two semi -bridge B, and so on. Figure 6 shows the application example of the entire bridge mode operation.

Under the parallel bridge mode, PWM-A controls the half-bridge A and half-bridge B, PWM-B to control the half-bridge C and D at the same time, instead of using PWM-C and PWM-D pins (recommended Ground). Bridge A and Bridge B are synchronized internally (even during the CBC), so as a bridge C and D, output A and output B should be connected together, and output C and output D should be connected together after a small output induction device. Essence Figure 7 shows an example of the connection of parallel bridge mode.

The pattern pins are configured as CBC flow limit operation in Figure 6 and Figure 7.

DRV8402 can also be used for three -phase permanent magnet synchronous motor (PMSM) application. Because each semi -bridge has an independent power and ground pins, a parallel resistor can be inserted between PVDD to PVDD_X or GND to GND_X. It is recommended to install a high -voltage side parallel -side resistor between PVDD and PVDD_X for differential current sensors, because high bias pressure on low -side sensing may affect the operation of the device. For three -phase application, it is recommended to use the OCL mode. Figure 8 shows a three -stage application example.

It is recommended that each application (not displayed in the figure) is deserted to the indulgence capacitor near each power.

Thermal information

DRV8402 provided by the heat enhancement packaging design as a hot interface compound (such as the North Pole Silver, Timtronics 413, ceramic thermal compounds, etc.) directly connected to the radiator. The radiator then absorbed heat from the integrated circuit and coupled it into a local air.

Hot Information

Rθja is a systematic thermal resistance from the joint to environmental air. Therefore, it is a system parameter containing the following components:

Rθja (the thermal resistance from the connection to the shell, or the hot segment in this example)

# 8226; thermal oil resistance

Heat resistance of the radiator

Thermal resistance of thermal lubrication can be according to the exposed heat segment plug area and the area of u200bu200bthe heat conductor manufacturer ( It is represented by ° C-in2/W or ° C-MM2/W). The approximate size of the exposed heat section is as follows:

DRV8402, 36 -pin PSOP3 ... 0.124 IN2 (80 mm2)

[12] [12]3] The thermal resistance of the thermal pads is considered to be higher than the thin hot lubricating fat layer.The heat resistance of the tape is even higher, and it should not be used at all.The thermal resistance of the heat sink is predicted by the radiator supplier, using continuous liquid dynamics (CFD) model modeling or measurement.

Therefore, the system RθJa RθJC+heat conduction lipid resistance+heat sink resistance.

For more heat information, see TI application report, IC packaging heat measurement (SPRA953A).

]