Functional applications

12 -bit dual transmission DAC

200 msps update rate

Single power supply: 3.0 V v -3.6 v

High SFDR: 85 DBC, 5 MHz

High IMD3: 78 DBC, 15.1 and 16.1 MHz

#8226 WCDMA ACLR: 30.72 MHz at 70 db

Independent or single -resistance gain control

dual data or cross data

#8226 1.2-v benchmark on the film

Low power: 330 MW

power failure mode: 15 MW

packaging : 48-needle TQFP

Application

Honeycomb base station transmission channel launch channel

—CDMA: W-CDMA, CDMA2000, IS-95

]-Tdma: GSM, IS-136, Edge/UWC-136

Medical/Test Instruments

Any waveform generator

Direct Digital synthesis (DDS)

cable modem terminal system (CMTS)

Instructions

dac5662 [123

] It is a single -chip dual -channel 12 -digit high -speed digital modulus converter (DAC) with a reference voltage in the chip.

The update rate of DAC5662 is as high as 200 millisecond/second, and has excellent dynamic performance and close gain and offset matching. These characteristics make it suitable for I/Q baseband or direct intermediate frequency communication applications.

Each DAC has a high impedance differential current output, which is suitable for single -end or differential analog output configuration. The external resistor allows the full -scale output current of each DAC alone or together, usually between 2 mA and 20 mA. The accurate in -chip benchmark voltage is compensated by temperature and provides a stable 1.2V reference voltage. Alternatively, you can use external reference.

DAC5662 has two 12 -bit parallel input ports with independent clocks and data locks. For flexibility, DAC5662 also supports each DAC reuse data on one port when operating in the interwoven mode.

DAC5662 is specially designed for 50Ω dualDifferential transformer coupling output of the end load. For the 20 mAh full-standard output current, support the 4: 1 impedance ratio (generated 4 DBM output power) and the 1: 1 impedance ratio transformer (-2 DBM output power).

DAC5662 provides 48 -pin thin square flat packaging (TQFP). The pin compatibility between members of the series provides 12 -bit (DAC5662) and 14 -bit (DAC5672) resolution. In addition, DAC5662 is compatible with DAC2902 and AD9765 dual DAC pins. The feature is characterized by the industrial temperature range of -40 ° C to 85 ° C.

Typical features

Digital input and fixed timing Digital input

DAC5662 data input port acceptance standards are accepted. Data bit D11 is the highest effective position (MSB). The converter output supports a clock rate of up to 200 millisecond/second. The best performance is usually achieved through symmetrical writing and clock duty cycle; however, as long as the timing specification is met, the duty cycle may be different. Similarly, settings and maintenance time can be selected within its specified restrictions.

All digital inputs in DAC5662 are compatible with CMOS. Figure 16 and 17 show the schematic diagram of the equivalent CMOS digital input of DAC5662. 12 -digit data input follows the dual dual encoding scheme. DAC5662 is designed to work under the digital power (DVDD) of 3V to 3.6V.

Input interface

DAC5662 with two working modes of the pattern pin selection, as shown in the table below: For the dual bus input mode, the device is basically composed of two independent DACs. Each DAC has its own independent data input bus, clock input and data writing signal (data lock).

In a single bus cross mode, the data should be displayed at the bus in the bus channel. In this mode, the Q channel is not used in the bus. The clock and writing input are now shared by two DACs.

Double bus data interface and timing

In the dual bus mode, the pattern pins are connected to the DVD. The two converter channels in the DAC5662 consist of two independent 12 -bit parallel data ports. Each DAC channel is controlled by its own groups (WRTA, WRTB) and clocks (CLKA, CLKB). WRT line control channel input lock memory, CLK line control DAC locks. The data is first of all from the WRT lineLoad the rising edge to the input lock.

Internal data transmission requires correct writing and clock input sequence, because the clock domain with the same cycle (but may be different) is actually input to DAC5662. This is defined from the minimum requirements between the clock rising edge and the writing input rising edge. This essentially means that the rising edge of the CLK must appear at the same time or before the rising edge of the WRT signal. If the clock rising edge occurs after the rising edge is written, it should be delayed at least 2 ns. Note that when the clock and the writing input are connected to the outside, these conditions are met. Note that all specifications are measured in the case of the WRT and CLK lines.

Single bus cross -data interface and timing

In the single bus staggered mode, the pattern pins are connected to DGND. Figure 19 shows the sequence diagram. In the staggered mode, I and Q channel sharing input (WRTIQ) and update clocks (CLKIQ and internal CLKDACIQ). Multi -way reuse logic orientation is directed to the input word on the I channel input to the I channel input lock (SELECTIQ high) or Q channel input locks (SELECTIQ low). When selectiq is high, the data value in the Q -channel lock memory is retained by reaping the output data of the locks to it again. When Selectiq is low, the data value in the I channel locks is retained by presenting the data output data to the input terminal.

In the interwoven mode, the I channel input data rate is twice the DAC core update rate. In the dual bus mode, it is important to maintain the correct order of writing and clock input. The edge trigger locks the LAND and Q channel input words to the rising edge of the input (WRTIQ). These data show the i and Q-DAC memory in the lower edge of the input. Before entering the DAC5662 clock to the DAC memory, divide it to coefficient 2.

The correct pairing of i and Q channel data is completed by resetiq. In the staggered mode, the clock input CLKIQ is divided by the second, which will be converted into the non -confirmed relationship between CLKIQ and CLKDACIQ rising edges. However, ResetIQ ensures that the correct position of the CLKDACIQ rising along the data of the data input at the DAC memory input is determined. When ReseTiq is high, CLKDACIQ is disabled (low).

Operation theory

The architecture of DAC5662 uses current control technology to achieve rapid switching and high update rates. The core component in a single DAC is a segmented current source array, which is designed to provide a full range output current of up to 20 mAh. The internal decoder addresss the differential current switch when the DAC is updated, and through the steering output output and the node IOUT1 and IOUT2 forms a corresponding output current. The complementary output provides the differential output signal. Compared with the single -end operation, the dynamic performance is doubled by reducing the occurrence of occasional harmonic, co -mode signals (noise), and peak -to -peak output signals.

The segmented structure has significantly reduced the fault energy and improved the dynamic performance (SFDR) and DNL. The current output maintains a very high output impedance greater than 300 k #8486;

When the GSET is high (single resistance mode), the full standard output current of the two DACs is determined by the internal reference voltage (1.2 V) and the ratio of the external resistor RSET connected to Biasj #273; A Essence When the GSET is low (dual -resistant mode), the full standard output current of each DAC is determined by the internal reference voltage (1.2 V) and the independent external resistor RSET connected to the BIASJ_A and BIASJ_B. Iref is multiplied by the internal multiplier coefficient 32 to generate an effective DAC output current. The range can be from 2 mA to 20 mA, depending on the resource set.

DAC5662 is divided into digital parts and simulation parts, and each part is powered by its own power pins. The number parts include the input locks and decoder logic of the edge, and the simulation part includes the current source array and its related switches and reference circuits.

DAC transmission function

Each DAC in DAC5662 has a set of complementary current outputs, iOUT1 and IOUT2.满标度输出电流IOUTFS是两个互补输出电流的总和：

单个输出电流取决于DAC代码，可以表示为：

[123 ]

The code is the decimal representation of the DAC data input word. In addition, IOUTFS is a reference current Iref function, which is determined by the reference voltage and external setting resistor (RSET).

In most cases, the complementary output drive resistor load or terminal transformer. The signal voltage of each output terminal is based on:

The load resistance value is limited by the DAC5662 output compliance specification. In order to maintain the specified linear performance, the voltage of iOut1 and IOUT2 u200bu200bshould not exceed the maximum allowable compliance range.

The total differential output voltage is:

DAC5662 provides two complementary currents Output, iOUT1 and IOUT2. Figure 20 shows the simplified topology of an analog class output. The output impedance of iOut1 and IOUT2 u200bu200bconsolidates the parallel combination of differential switches, current sources and related parasitic capacitorsFormed.

The signal voltage swing generated at the two output end IOUT1 and iOUT2 is limited by positive and negative convergence. The negative limit-1V is given by the breakdown voltage of the CMOS process. Specifies that exceed this limit will damage the reliability of the DAC5662 and even cause permanent damage. When the full margin output is set to 20 mA, the positive rules are equal to 1.2 volts. Please note that for the selected output current iOutfs u003d 2 mAh, the scope of compliance is reduced to about 1 volt. It should be noted that the configuration of the DAC5662 does not exceed the range of softness to avoid distortion performance and integral linearity degradation.

The best distortion performance is usually implemented at a maximum full -scale output signal restricted at about 0.5VPP. This is the case for the 50Ω dual -end load and the 20 -mAh output current. By selecting the appropriate transformer and maintaining the optimal voltage level of iOUT1 and IOUT2 u200bu200bat the same time, various loads can adapt to the output of DAC5662. In addition, the combination of differential output configurations with transformers will help achieve excellent distortion performance. Common model errors, such as occasional harmonics or noise, can be greatly reduced. This is especially true in the case of high output frequency.

For applications that require the best distortion and noise performance, it is recommended to choose a full standard output of 20 mAh. For applications that require low power consumption, you can consider the low full range range of 2 mA, but it can tolerate the slight decrease in performance level.

Output configuration

The current output of DAC5662 allows multiple configurations. As mentioned earlier, the optimal dynamic performance is generated using the differential output of the converter. This differential output circuit can be composed of RF transformer or differential amplifier configuration. The transformer configuration is the ideal configuration of most AC coupling applications, and the operational amplifier will be suitable for DC coupling configuration.

For applications that require single -pole output voltage, you can consider single -end configuration. Convert a resistor from any output end and convert the output current into a ground reference voltage signal. In order to improve DC linearity by maintaining virtual grounding, I-TO-V or op amp configuration can be considered.

Transformer differential movement

A convenient way to convert the difference output signal into a single -end signal using the radio frequency transformer, while achieving excellent dynamic performance. Select the appropriate transformer carefully according to the output spectrum and impedance requirements.

The advantage of the configuration of the differential transformer is to significantly reduce the co -mode signal, thereby improving the dynamic performance in the wide frequency range. In addition, by selecting the appropriate impedance ratio (winding ratio), the transformer can be used to provide the best impedance matching, and at the same time control the compliance voltage of the converter output.

FIG. 21 and FIG. 22 shows the configuration of the impedance ratio of 1: 1 and 4: 1, respectively. Note that the central tap of the transformer input must be ground to enable DC current. Apply 20 mAh full marking outputThe current will cause the 0.5-VPP output of the 1: 1 transformer and the 1-VPP output of the 4: 1 transformer. Generally speaking, the output distortion of the 1: 1 transformer configuration is slightly better, but the output power of the 4: 1 transformer will be 6DB higher.

Single -end configuration

FIG. 23 shows a single -end output configuration, where the output current iOUT1 flows into the equivalent load resistance of 25 #8486;. The node IOUT2 u200bu200bshould be connected to agng or connected to AGND with a resistor with 25 #8486; When the output current of 20 mAh is applied, the rated resistor load of 25 #8486; the differential output motion of 1VPP is generated.

Reference operation

Internal reference

DAC5662 has a film reference circuit, including the 1.2V band gap benchmark and two control amplifiers , Each DAC. DAC5662's full standard output current iOUTFS is determined by the value of the reference voltage VREF and the resistor RSET. IOUTF can be calculated through the following formulas:

Reference control amplifier work as a V-I converter to generate a reference current IRef. Iref is determined by the ratio of VREF and RSET (see equivalent format 9). The full marked output current IOUTFS is obtained by Iref by a fixed factor 32.

When using internal reference, 2-k #8486; resistance value can generate a full standard output of about 20 mA. Considering a resistor with a tolerance of 1%or higher. Choose a higher value, the output current can be adjusted from 20 mA to 2 mAh. For reasons to reduce total power consumption, improve distortion performance, or observe the output compliance voltage restrictions under the given load conditions, it may be desirable to operate DAC5662 under the output current below 20 mAh.

It is recommended to use 0.1 μF or higher ceramic chip capacitor to bypass Extio pin. Control the internal compensation of the amplifier, and its small signal bandwidth is about 300 kHz.

External reference

You only need to apply an external reference voltage on the EXTIO pin to disable the internal benchmark. In this case, the Extio pins play a role in input. For applications that require higher accuracy and drift performance or increase the control capacity of dynamic gain control, you can consider using external benchmarks.

Although the 0.1-μF capacitor is recommended to use the internal benchmark, the capacitor is optional for external benchmark operation. Reference Extio has high input impedance (1 m #8486;), which can be easily driven by various power supply. Note that the voltage range of the external benchmark should be kept within the conformity range of the input input.

gain setting options

The full standard output current on the DAC5662 can be set in two ways: separate each channel settings in two DAC channels, or set up two channels at the same time. For the independent gain setting mode, the GSET pin (pin 42) must be low (that is, connected to Agnd). In this mode, two external resistors need to be connected to the BIASJ U A pin (pin 44), and the other is connected to the BIASJ U B pin (pin 41). In this configuration, users can flexibly set and adjust the full standard output current of each DAC, allowing compensation for the possible gains that may be matched in other places in the transmitting signal path.

Or, make GSET pin high (that is, connect to AVDD), DAC5662 switch to synchronous gain setting mode. At present, the full standard output current of the two DAC channels is determined by only one external RSET resistor connected to the Biasj U A pin. The resistor at the biasj_2 pin can be removed, but this is not necessary, because the pin does not work in this mode, and the resistor does not affect the gain equation.

Sleep mode

DAC5662 has a power -off function. If there is no clock, you can use this function to reduce the total power current to less than 3.5 mA within the specified power supply range. Apply a logical power loss mode on the dormant pins, and the logic is lowered to use the normal operation. When it is not connected, the internal pull -down circuit can make the converter work normally.

Mechanical data

Note: A. All linear size units are all millimeters.

B. This drawing will not be notified separately if there is any change.

C, belonging to Jedec MS-026