The ISL6550 is an accurate, flexible, VID code controlled reference and high-end microprocessor voltage monitor and memory power supply. It monitors various input signals and supervises the system (usually a DC/DC converter) and its output signals. Block diagram reference. The ISL6550 includes a 5-bit DAC (Digital-to-Analog Converter), which is programmed by five VID inputs. The voltage range of the BDAC (buffered DAC output) determines the large pool and the DACLO voltage level, through an externally adjustable voltage divider network with resistors R1, R2, R3. VREF5 is a precision trimmed 5V reference that is a resistive top divider used to set the voltage. Programmable window comparators monitor overvoltage (OV) and undervoltage (UV) levels. The OVUVSEN input, usually from the associated power converter device monitors and compares the BDAC; the error band is established by the R4 and R5 resistors set on the OVUVTH pin. An optional external capacitor on the UVDLY pin gives a programmable delay to UV. High-gain op-amp pins VOPP, VOPM, VOPOUT; allow, it can be used as a gain stage to monitor different voltages with BDAC levels. The PEN (Power Enable) input, driven from an opencollector source, enables (when logic high) the output of an external converter, via PGOOD or enables the output (both open drain). They all basically indicate that the power supply is enabled (PEN=HIGH) and there is no fault condition. There are two logics to choose from that determine the startup and PGOOD states; block a more detailed diagram or a logic options table. These two logical options determine ordering information with a suffix letter A or C.