74LS90: Decimal Counter; Twelve Divide Counter; 4-Bit Binary Counter
SN54/74LS90, SN54/74LS92 and SN54/74LS93 high-speed 4-bit ripple type counters, divided into two parts. Each counter has a divide-by-two and a divide-by-five (LS90), divide-by-six (LS92) or divide-by-one (LS93) sections that are triggered by a high-to-low transition on the clock input. Each section can be used individually, or tied together (ask CP) to form a BCD, bidirectional quintuple, modulo 12 modulo 16 counter. All counters have a 2-input gated master reset (clear), and the LS90 also has a 2-input gated master set (preset 9).
Features:
• Low power consumption. Typically 45 MW • High count rate. Typically 42 MHz • Counting mode selection. BCD, Double Five, Divide by Twelve, Binary Input Clamping Diode Limits High Speed Termination Effectiveness Pin Name Loading (Note a)
High Medium Low
CP0 clock (low edge) input 0.5 UL 1.5 UL
CP1 clock (low edge) input 5 groups (LS90) 6 groups (LS92) 0.5 UL 2.0 UL
CP1 clock (low edge) input 8 sections (LS93) 0.5 UL 1.0 UL
Master reset (clear) input for MR1, MR2 0.5 UL 0.25 UL
MS1, MS2 main setting (preset 9, LS90) input 0.5 UL certified 0.25 UL
Q0 output 2 groups (Note B & C) 10 UL 5 (2.5) UL
Q1, Q2, Q3 output 5 (LS90) 6 (LS92) 8 (LS93)
Section (Note b) 10 UL 5(2.5) UL

Precautions:
A. 1 TTL unit load (UL) = 40 mA HIGH/1.6 mA LOW.
B. Output low drive factor is 2.5 UL military, (54) and 5 UL commercial (74) temperature range.
C. Q0 output guaranteed to drive full fan-out plus CP1 input device.
D. To ensure proper operation the rise (TR) and fall time (TF) of the clock must be less than 100