Product Details

describe:

The ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6 GSPS analog-to-digital converters (ADCs). Low power consumption, high sampling rate and 12-bit resolution make the ADC12xJ1600 ideal for a variety of multi-channel communication and test systems.

A full power input bandwidth of 6 GHz (-3 dB) enables direct RF sampling in both L-band and S-band.

Many clocking functions are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with the AD7863BR-3 integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. Provides time-stamped inputs and outputs for pulsed systems.

The JESD204C serial interface reduces system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support 2 to 8 lanes (dual- and quad-lane devices) or 1 to 4 lanes (for single-lane devices), and SerDes baud rates up to 17.16 Gbps, providing the best configuration for each application.

characteristic:

●ADC core:

- Resolution: 12 bit

—Maximum sample rate: 1.6 GSPS

—Non- interleaved architecture

- Internal jitter reduces higher harmonics

●Performance Specifications (–1 dBFS):

— Signal-to-noise ratio (100 MHz): 57.4 dBFS

— ENOB (100 MHz): 9.1 bits

— SFDR (100 MHz): 64 dBc

— Noise Floor (–20 dBFS): –147 dBFS

●Full scale input voltage: 800 mV PP-DIFF

●Full power input bandwidth: 6 GHz

●JESD204C serial data interface:

— Supports 2 to 8 (quad/dual channel) or 1 to 4 (single channel) total SerDes channels

—Maximum baud rate: 17.16 Gbps

— 64B/66B and 8B/10B encoding modes

- Subclass 1 support for deterministic latency

— Compatible with JESD204B receivers

● Optional internal sample clock generation

—Internal PLL and VCO (7.2–8.2 GHz)

● SYSREF windowing simplifies synchronization

● Four clock outputs simplify system clocking

— Reference clock to FPGA or adjacent ADC

— Reference clock for SerDes transceivers

● Timestamp input and output of pulse system

●Power consumption (1 GSPS):

— Four channels: 477 mW/channel

— Dual channel: 700 mW/channel

—Single channel: 1000 mW

●Power supply: 1.1V, 1.9V

parameter:

Sample Rate (Max) (MSPS): 1600

Resolution (bits): 12

Number of input channels: 1

Analog Input Bandwidth (MHz): 6000

Features: Super high speed

Input range (Vp-p): 0.8

Power consumption (typ.) (mW): 1000

Architecture: Folding Interpolation

Signal-to-noise ratio (dB): 57.4

ENOB (bits): 9

SFDR (dB): 66

Operating temperature range (°C): -40 to 85

Input buffer: yes