Features

Single -chip microcomputer test signal generator

buffer voltage output

High performance:

] –Thd: –125 DB (G 1/1 to 1/8)

-Sto signal ratio: 120 dB (413 Hz BW, G 1/1)

# 8226; Simulation and digital gain control

Output frequency: 0.488 Hz to 250 Hz

Sine, pulse and DC mode

#8226 Digital data input mode

Low -conducting resistance signal switch

synchronous input

123] Simulation power supply: 5 v or ± 2.5 v

Digital power supply: 1.8 v to 3.3 v

Power: 38 MW [123 [123 ]

Packaging: TSSOP-24

working range: -50 ° C to+125 ° C

# 8226; Energy exploration

Seismic monitoring system

High -precision instrument

DAC1282 [123

] It is a completely integrated digital model converter (DAC) that provides low distortion and digital synthetic voltage output, which is suitable for seismic equipment testing. DAC1282 has achieved very high performance in low -power small packages. These devices and high -performance ADS1281 and ADS1282 modulus converter (ADC) together constitute a measuring system that meets the strict requirements of seismic data collection equipment.

DAC1282 integrates digital signal generators, DAC and output amplifiers, providing sine waves, DC and pulse output voltage. Simulation and digital output are programmable output from 5.0 Hz to 250 Hz. The simulation gain can be adjusted in the 6DB step, and the digital gain can be adjusted in the 0.5DB step. The simulation gain setting matches the settings of ADS1282 to test all the gains of high -resolution.

DAC1282 also provides pulse output. The pulse amplitude is programmed by the user, and then the pin is selected accurately. The custom output signal can be generated by applying an external bi current mode.

Signal switch can be used to connect DAC output to sensors for THD and pulse tests.The switch is controlled by pins and commands.

Synchronous pipe pin synchronizes the DAC output with the modulus converter (ADC). The power -off input will disable the device, which reduces the power consumption to micro tiles.

Typical features

TA +25 ° C, AVDD +2.5 V, AVSS --2.5 V, DVDD 3.3 V, FCLK 4.0966 MHz, VREF 5 V, unless there is another explanation. DAC1282A only supports gain 1/1, 1/4, and 1/16.

Detailed description Overview DAC1282 is a single -chip digital mode converter (DAC), which can generate low -distortion of real string waves and pulse output signals to meet the high requirements of the earthquake record device. Figure 32 shows the frame diagram of DAC1282.

In addition to DAC1282A only supports PGA gains of 1/1, 1/4, and 1/16, the DAC1282A device is equivalent to DAC1282. DAC1282A also relaxes these gains of THD. For details, see the electrical characteristics section.

DAC1282 requires two power supply voltage: simulation and numbers. The simulation power supply can be a single 5V or bipolar ± 2.5 V. The range of digital power supply is 1.65 V to 3.6 V. The output signal co -mode voltage adjustment is adjusted to 100 MVs below the simulation power supply voltage. Internal power -power reset (POR) circuit is reset to DAC when calling.

A SPI #8482; -The compatible serial interface is used to access the DAC1282 register for equipment configuration and control. The configuration register can be read back by recording the data on the DOUT tube. The DAC1282 voltage output is the output of the full differential, and the output on the VOUTP/VOUTN pin. CAPP/CAPN pins are connected to an external filter capacitor to reduce the output noise.

Refer to the input voltage setting DAC1282 full marking output. Apply a DAC reference voltage between VREF and AVSS pins. After optimizing the DAC, it can work under the voltage of 5 volts. The sine wave generator can set the sine frequency and amplitude through the register program. The frequency range can be programmed from 0.4883 Herz to 250 Hz. The output level is controlled by analog gain (6 decibel steps in step) and digital gain (steps 0.5 decibels).

The digital modulator receives the output of a sine wave generator or 24 -bit DC register to generate a density bit flow. Bit flow drives the main DAC. Optional land, a density data can be lostDrive DAC directly, bypass the digital signal generator. The main DAC generates a differential output current, which is converted to a differential output voltage through internal current voltage (I/V) amplifier. The output range is set by analog gain, which can zoom in the DAC current generator. The output amplifier provides current limit protection.

DC mode is programmed by 24 -bit registers to provide DC output. The DC mode also has a programmable range controlled by analog gain control.

In the pulse mode, the 5 -bit pulse DAC that responded quickly was used to provide 31 preset DC levels. Within available output range. The pulse digital modulus is optimized to provide fast response and shorter output rising time. The pulse digital modulus is triggered by the synchronous tube foot and used to accurately control the pulse time.

DAC1282 includes an output switch of a low distortion. The output switch can connect the DAC1282 output to the sensor for THD and pulse testing. The switch is controlled by the pin or command, so the accurate switch is allowed to be fixed.

Synchronous input synchronizes the output signal with the time benchmark of known time. In the sine mode, SYNC reset the sine wave to zero. In the pulse mode, one of the DC levels of two user programming is selected synchronously.

Reset/PWDN pin closes the device when low voltage. When ReseT/PWDN is released at a high level, DAC1282 is reset.

SW/TD input is dual function. In digital data mode, the tube foot is density data input. In other modes, the SW/TD control switch is turned on/off.

FIG. 33 shows the main details of the main DAC. The main DAC provides digital modulus by filtering a density digital data. During the work, the current generator sets a range of range, which is mirrored to the multi -tap, and the current turns to the filter level. The current generator is controlled by an analog gain control register, and the register shrinks the weight of the tap current to one of the seven range (0 db to -36 dB).

When the digital input is sampled, the current control level switches the tap current to the positive or negative currents and nodes. One higher density guides one node to increase the average current than another node, thereby increasing differential current. Differential currents pass through the internal I/V conversioner level to differential voltage. The common modulus current source is balanced at the magnitude of the amplifier and the node.

Feature description

Signal output (voutp, voutn)

As shown in Figure 34, DAC is on the pin voutp and voutn Provide differential voltage (VDiff VOUTP -VOUTN). The output co -mode voltage (VCOM) is adjusted to the medium point of 100 MV in the medium point below the analog power supply (AVDD -AVSS).

Each signal output is swinging up and down in the co -mode voltageEssence Differential use of DAC output can get the best performance. In the power -off mode, the output enters the high -impedance 3 state mode.

Note: VDiff Voutp-Voutn ± 2.5 V × gain (vREF 5 V). VCOM - 0.1 V (± 2.5 V power supply) or 2.4 V (5 V power supply).

The rated value of the DAC output buffer is driven 2 -vosus capacitance load (maximum) and 100Ω resistor load (minimum value). However, the decrease in THD performance causes the resistance load to be less than 1kΩ, as shown in Figure 26.

Internal digital modulator generates signals to drive DAC. The modulator will be shaped with internal noise to high frequency, and frequent forming noise on DAC output. However, high -frequency DAC output noise is suppressed by ADC's digital filter and does not affect system performance.

DAC sampling update noise on the signal output. The sampling noise does not affect the ADC performance, but when testing the ADC is close to the full standard input, the noise will cause an error instruction for the ADC modulator to detect the overvasing range. When testing or lower than the ADC full -scale input, the ADS1282 over -range output signal indication should be ignored.

DAC mode

DAC1282 has four working modes: sine, DC, pulse and external digital data input. These modes are programmed by the Mode [1: 0] bit in the Ganmod register, as shown in Table 1.

Snuanars

In the sine mode, DAC1282 provides a sine wave output. The internal signal generator generates a sine wave signal. M [3: 0], n [7: 0] and FREQ register position programming the output frequency. The frequency range can be programmed from 0.4883 Hz to 250 Hz, as shown in equivalent 1.

where:

m [3: 0] ≤n [7: 0]

fclk 4.096 MM. The signal frequency is zoomed in FCLK.

Table 2 lists the value of the register M and N of the selected output frequency.

When the M or N register is updated, the sine wave is reset to zero point. The sine wave can also be reset to a zero -cross point, which is high by the synchronization pin; see the synchronous part.

The amplitude of the sine wave output is determined by analog and digital gain. The analog gain increase is 6 dB, from 0 db to -36 dB, and is programmed by the gain [2: 0] register. Table 3 lists analog gain.

(1), DAC1282A only supports simulation gains of 1/1, 1/4, and 1/16.

(2), compared to 1.77 VRMS.

(3), VREF 5 V, digital gain 0 db.

Digital gain resolution is increased by 0.5 decibels, from 0 decibels to full mute, and programming from a sine [7: 0] storage position. Table 4 lists digital gain settings. Formula 2 is the amplitude settings in a sine mode.

Sinlestess amplitude (DB) Simulation gain (DB)+Digital gain (DB)

For a given signal level, the best signal -to -noise ratio is to maximize the simulation gain and maximize Digital gains are achieved.

DC mode

DAC1282 offers 24 -bit DC output mode with resolution. The output level is determined by analog gain and 24 -bit DC register.

gain [2: 0] Setting analog gain (see Table 3). DCG [23: 0] The storage position sets the 24 -bit level in the selected simulation range. Table 5 lists digital gain settings in DC mode.

Pulse mode

In the pulse mode, the 5 -bit pulse DAC that responded quickly to generate output. The pulse digital modular converter is designed as an output function similar to the linear unit DB, allowing the pulse test signal within all range. Two registers are used to preset DAC output. Synchronous pins are used to select one of the two registers. When SYNC is low, the Pulsa storage value drives DAC; when Sync is high, the Pulsb register value drives DAC. The pulse sender is programmable to generate differential outputs of -2.5 V to +2.5 V. Please note that the pulse level is proportional to the VREF and has nothing to do with the simulation gain setting. Table 6 lists the programmable range of pulse A and pulse B register.

Note that when the pulse tests ADC, the time domain response of the ADC digital filter has a characteristic hypervisor and the bell. Because the ADC filter is overlooking, the input level close to the ADC full markedness may cause the ADC output code to cut waves.

Digital data mode

In the digital data mode, the DAC internal signal generator is bypass, and DAC is driven by applying a special current input. Apply customized digital data mode can generate any DAC output waveform. The data format in this mode is a density modulation input of CLK/16 data rate (256 kHz). The input is applied to the SW/TD input pin. DAC1282 output in digital data mode is defined in equivalent 3.

Digital data mode Differential output VOUTP -VREF/2 × gain × (TD -50%)/25%,

where: vREFNamed as 5 V, gain is analog gain (1/1 to 1/64), TD is a density of special flow, from 25%to 75%.

DAC1282 filtering digital data (Bit flow) input, which provides voltage output proportional to the density of the biochemical flow. Investment [2: 0] The register sets an analog gain in a step -length settings of 6 decibels, from 0 decibels to -36 decibels (1/1 to 1/64). For external timing requirements, see the synchronization part. Table 7 lists a few values u200bu200bin the external flow input.

Reference voltage (VREF)

DAC1282 requires external reference to operate. Although the reference voltage as low as 2.5V, the 5V reference voltage can get the best signal -to -noise ratio. Reference Input is defined as a voltage difference between VREF and AVSS (ie vREF VREF -AVSS). The DAC1282 output is shar with VREF; therefore, reference noise or drift appears on the DAC output. The reference noise conference has led to a decline in signal -to -noise ratio. It is recommended to use low drift and low noise benchmark.

Use a star -shaped connector to connect the external reference ground pins directly to the AVSS pin 14. Star -shaped connections minimize the possibility of the power string disturbance. In addition, a 0.1-μF capacitor is connected near the VREF and AVSS terminals to reduce noise sensitivity. Figure 35 shows the reference connection. Reference input impedance is 220k #8486;. The switch is turned off during power off, resulting in a very high input impedance. For single -power applications, connect AVSS to a clean simulation location.

(1), the proposed bypass electric container.

Output filter (CAPP, CAPN)

CAPP and CAPN pins are the connection of two external capacitors, one capacitor is connected to CAPP and VOUTP, and the other capacitors are connected to CAPN and Voutn. Require capacitors to filter out DAC sampling noise. The capacitor value is 1 nf; a capacitor (C0G ceramic or film) should be used with a low voltage coefficient.

As shown in Figure 36, an external capacitor and internal feedback resistance form an analog low -pass filter. After the data is transformed in steps, DC, and digital data mode, the typical settings of DAC and analog filters are 100-μs, as shown in Figure 46. In the pulse mode, the internal invalidation of the filter generates a shorter stability time.

Output switch (SWINP, SWINN, SWOUTP, Swoutn)

DAC1282 has an integrated output switch. The switch can be used to test the DAC output signal routing to the sensor for pulse, THD, and co -mode testing. The switch has components of low -conducting resistance and matching to minimize signal distortion. Switch input voltage rangeExtend to analog power supply.

The switch is controlled by three registers position SW [2: 0], and it is also controlled by SW/TD input pin. When the register or SW/TD input control changes, the switch is integrated first and then combined. The SW/TD input can be used to force the switch to accurately control the vein test of the sensor; see the switch control/DAC data input (SW/TD) section. Figure 37 and 8 describe the switch operation.

Please note that when the DAC is in the power off mode, the switch is forced to open.

As shown in Figure 29, the connection resistance changes with the change of the switch signal level. When the switch is used to send a signal and a resistor load is connected to the switch output, the change of the switch connected to the resistance is interacted with the load resistance, resulting in THD decrease. Figure 27 illustrates the relationship between THD and switching load resistance. The correlation of THD data is obtained with a full -scale signal.

Clock input (CLK)

CLK pin is the main clock input of DAC1282, usually 4.096 MHz. As a high -performance clock source, high performance is essential. It is recommended to use a crystal oscillator or a low shake lock in the loop clock source. Make sure to avoid the shortcomings of the tracking and the source end (usually 50 #8486;) to avoid ringing at the input end. See the CLK specifications shown in Figure 38 and Table 9.

Switch control/external digital input (SW/TD)

SW/TD is a multi -functional digital input pin. The SW/TD function depends on the operation mode.

Software function

In sine, DC and pulse mode, SW/TD controls the output switch. When SW/TD is low, all switches are forced to open, covering the switch register settings (SW [2: 0]). When SW/TD is high, the switch is transparent to the register setting value. In the power -off mode, the switch is forced to open.

TD function

In digital input mode, SW/TD is used to drive the signal input of DAC. The data input is modulated by a density and the clock is input by the main clock (CLK). When the density is 75%(that is, three -quarters of the average is 1 ), the output voltage is positive to the maximum value. When the density is 25%(that is, three -quarters of the average is 0 ), the output voltage is negatively maximized. When the one density is 50%(average, the number of 0 and 1 is equal), the difference output is zero.

SW/TD is sampled by DAC1282 at a CLK/16 rate. Therefore, the uncertainty of sampling can have a ± 8 CLK cycle. Synchronization can eliminate uncertainty by synchronizing SW/TD to the expected CLK cycleEssence Synchronous digital input will cause the output signal to be consistent; see the synchronous part.

The output range is set by analog gain position, gain [2: 0]; see Table 3. Formula 3 describes the relationship between DAC output and Bit flow input density. Make sure to avoid the short -term tracing to avoid the bell at the input terminal. In some cases, the source connection (20Ω to 50Ω) may be needed.

Synchronous

synchronization is a digital input used for synchronous DAC1282 output.

In digital data mode, DAC input is a 1 -density bit flow. In this mode, the sampling of SW/TD digital data is synchronized with the required main clock cycle (CLK). When SYNC is low or high, DAC works normally. When synchronization from low to high, the DAC output is reset to zero, and the sampling of the SW/TD is reset into the subsequent eighth rising CLK edge. Then sample SW/TD regularly at the subsequent 16 CLK interval. After synchronization, the DAC output is not set, and complete settings are implemented after the 400 CLK cycle, as shown in Figure 39.

In the sine mode, the synchronous ascending edge resets the DAC output to the difference 0 V (sine waves over zero). When sync is high or low, the output is not affected. When synchronization from low to high, the output is reset at the following clock ascending. Synchronization must be in a low pulse state within at least 2 CLK cycles. Synchronous ADC and 128ADC in synchronous ADC mode.

To synchronize DAC, follow the CLK timing requirements shown in Figure 40. In other words, the synchronous ascending edge should be applied before or after the setting time or after the time specification. If it does not meet the synchronous timing requirements, the DAC may be synchronized with timing errors with a clock cycle.

In the pulse mode, the synchronous pins select one of the two pre -programmed pulse levels. Pulse levels can be programmed from +2.5 V to -2.5 V in a step-by-time steps of Pulsa and Pulsb through the pulse level registers. When the SYNC value is low, the value of the Pulsa register is driven by DAC; when the SYNC value is high, the value of the Pulsb register is the code of the DAC, as shown in Figure 41. When the synchronous pipe foot is changed, the DAC output is immediately updated to the new code.

reset/pwdn

Reset/PWDN is a digital input for closing and resetting DAC1282. To disconnect DAC's power, lower your pins. In the power -off mode, the power consumption is reduced to the leakage level of the device (see the electrical characteristic table). Signal output and digital pins output enter the 3 state, and the output switch is closed. Note that digital input must be defined as low logic or high logic; noTo float input. Disable CLK input to minimize leaks. To exit the power, put your pins at a high position. After exiting the power generation mode, the DAC1282 reset.

DAC1282 is reset by reserving the RESET/PWDN pin at least two FCLK cycles, and then returned to the high level. DAC1282 keeps resetting 2 FCLK cycles; after this time, DAC communication may begin, as shown in Figure 42 and Table 12.

AVDD, AVSS and DVD power supply

DAC1282 has two power supply: simulation and numbers. The simulation power supply (AVDD, AVSS) is 5 V, which can be a single 5 V or a dual power supply (± 2.5 V). The simulation power should be cleaned, no noise and ripples. DAC1282 adjusts the output co -mold voltage to 0.1 V. 0.1 V. Due to the current consumption signal -related current, and the internal sharing reference input internal sharing in AVSS (pin 14), the tracking resistance between AVSS (pin 14) and AVSS power supply should minimize, otherwise the performance may be reduced. Therefore, using a star connection to connect the external reference ground to the device AVSS terminal. This configuration helps minimize power and reference input coupling.

DVDD is a digital power supply for internal numbers and equipment I/O pins. The allowable range of DVDD is 1.65 to 3.6 volts.

The power supply can be connected or disconnected in any order, but the analog or digital input does not exceed AVDD, AVSS or DVDD, respectively. In this case, the internal ESD protection diode may start conducting electricity. The input current must always be limited by the absolute maximum rated value table.

At the time of power, when the latter of the DVDD exceeds about 1.3V, or the difference between the AVDD – AVSS exceeds approximately 1.4V, the internal power reservation (POR) occurs. During the POR period, as shown in Figure 43, the device remained in a reset state within the 216 FCLK cycle. During this period, the DAC1282 output remained at 0 V, the difference. SPI communication cannot be performed during this period. After the resetting time, the default settings are loaded: 31.25 Hz, 28 MVRMS amplitude, and the output is closed. Then you can start SPI communication.

Power consumption

DAC1282 consumption power depends on the simulation gain. Table 13 shows DAC power consumption.

Disposal and gain error

DAC1282 has low offset errors (± 7/gain+50 PPM FS typical values) and low gain errors (0.1 %Typical value). DAC1282's offset and gain drift are also very low. Calculation method of using Formula 4Calculation drift:

Drift calculation (maximum-minimum)/temperature range (PPM/° C), where: Max and min are recorded in the specified temperature range of -40 ° C to+85 ° C, respectively. The maximum and minimum offset and gain error (unit: PPM).

The gain matching is the gain error of all simulated gains, gain 1/1.

signal -to -noise ratio (SNR)

DAC1282 has excellent signal -to -noise ratio (SNR) performance. The signal -to -noise ratio data is obtained by the data captured by the DAC circuit in Figure 50 and the ADS1282.

The signal-to-noise ratio is measured at -0.5dbfs and a test frequency of 31.25Hz, and then uses a complementary gain to the 4096 data points from ADS1282 to fast Fourier transformation (FFT). The noise power is calculated on the bandwidth of the 413 Hertz (1 millisecond sampling cycle). In order to calculate the signal -to -noise ratio, DC and Kiso Harmony is removed. The signal -to -noise ratio measurement represents a combination of signal -to -noise ratio of ADS1282 and the signal -to -noise ratio of DAC182.

DC noise

Use DAC circuits in Figure 50 to obtain DC noise data, data captured by ADS1282. Measure the noise in DC mode, and the output voltage is set to 0 V differential. The ADC gain setting is a complement of the DAC gain of each output range. The noise is the standard deviation of the 4096 -point ADC collection record (both square root noise, reference output).

Total harmonic distortion (THD)

DAC1282 achieves excellent THD performance. THD data is obtained by the DAC circuit in Figure 50 and captured by ADS1282. The ADC gain setting is a complement of the DAC gain of each output range.

THD uses-0.5-DBFS output signal level and 31.25-Hz test frequency measurement, and then perform FFT for 4096 ADC collection records. The ADC data point increased to 16384, and the gain was 1/16, 1/32, and 1/64 to improve the harmonic reproduction caused by higher noise flooring. THD measurement value represents a combination of ADS1282 THD and DAC1282 THD.

Step response

DAC's step response depends on the mode. In the pulse mode, DAC disables external analog filters formed by capacitor CAPP and CAPN. The disability to disable the simulation filter with the fast response pulse DAC will significantly speed up the rise time and shorten the setting time. Note that the additional filter component in the signal path may also affect the response time.

FIG. 44 shows the pulse mode jump response after the synchronous pipe foot conversion. Figure 45 shows that after the synchronous tube foot is converted, the pulse mode details are set to 0.1%of the final value.

FIG. 46 shows the step response time of the DC mode. The steps of sine and digital patterns have similar stability time. Note that the additional filter component in the signal path may also affect the response time.

The frequency response

The internal signal generator of the DAC can output the signal frequency of 0.489 Hz to 250 Hz. By using the external digital input (bit flow) to directly drive the DAC, you can also get the frequency beyond this range. However, the DAC low -pass filtering number inputs and generates the SINX/x frequency response. The -3 DB signal bandwidth of DAC filter is 8.2 kHz. Figure 47 shows the frequency response of the DAC1282. Please note that the digital input of high -end noise shapes may limit the available frequency range due to increased noise.

Device function mode

Serial interface

DAC configuration is through a SPI compatible serial interface. Four signals composition: CS, SCLK, DIN, and DOUT; or the interface can consist of three signals. In this case, CS can be low. Binding CS low permanent choice device and DOUT is still a driver output. The interface is used to read and write registers, and also uses the DAC reset command.

Serial communication

DAC1282 communication is achieved by the register data input device (on DIN) and read back register data (on DOUT). The SCLK input is used to timing the data of the in -and -out device. Data rose along the line in the serial clock (SCLK), and the output of the SCLK decrease is output. The communication protocol is semi -double (that is, the data is transmitted from one direction to the device at a time).

The communication with the device occurred on the 8 -bit boundary. If the SCLK conversion occurs accidentally (for example, the noise peak may be caused), the DAC1282 command decoder may not be synchronized, and the serial port may not be able to respond correctly. The serial port can be replaced through one of the following methods:

1. Raise the CS and reset the interface;

2. Keep the SCLK not active (low state) 218 u200bu200bFCLK cycle, in order to use it Automatic resetting interface (see the SPI timeout part);

3. Set the reset/pwdn as a low position, and then return to the high position to reset the device and interface;

4. The circulating power supply is Put the power -on reset (POR).

chip selection (CS)

CS (chip selection) selected DAC1282 for communication. To choose the device, pull the CS low. The duration of the CS command must remain at a low position. When the CS is high, the serial interface is reset, the input command is ignored, and DOUT entersEnter high impedance status.

Serial clock (SCLK)

Serial clock (SCLK) is a Schmidt triggered input to input and output data to DAC1282. SCLK can be high or sluggish. If SCLK is at a low speed, the SPI timeout function is in a state of activity. If SCLK is at a high idling speed, the SPI timeout function will be disabled.

Although there are built -in Schmitt triggers, keep SCLK clean as possible to prevent small faults from accidentally moving data.