Features

Directly measured 64 single -chip microcomputer solution low level current

high precision verified, real integration 100%charging structure [123 123 ]

Easily upgrade application for the existing DDC series

Extremely low power: 3MW/channel

polar linear: import read number of read numbers ± 0.025%± 1.0ppm fsr

Low noise: fsr 6.3ppm

Rest -speed

- The data rate is as high as 6KSPS, 20 -bit performance

-Mori -micro integration time is as low as 160

123] Packaging inside the cross -road capacitors simplified PCB design

Application

CT scanner

Optical diode sensor [123 123

]

X -ray detection system

Instructions

DDC264

is a 20 -bit, 64 channel, current input mold number converter. It combines the current voltage conversion and A/D conversion, so that 64 independent low -electric flat current output equipment, such as photoelectric diode, can directly connect to its input terminal and digitize.

For each of the 64 input terminals, the DDC264 uses the verified dual -switch points front end. This configuration allows continuous current points: When one integror is digitized by the A/D converter of the board, the other integrifice points the input current. This structure provides a very stable offset and loss -free input current collection. The adjustment range from 160 μs to 1s is allowed to continue to measure the current from FAS to μAS with excellent accuracy.

DDC264 has a serial interface, which is designed for the chrysanthemum chain in the multi -device system. Just connect the output of one device to the input of the next device to create a chain. Ordinary clocks are powered on all equipment in the chain, so the digital overhead in the DDC264 system is the smallest. DDC264 uses+5V analog power and+2.7V to+3.6V digital power supply. The bypass container in DDC264 package helps to minimize the requirements of external components. DDC264 BGA-100 is encapsulated in the temperature range of 0 ° C to+70 ° C. There are two versions: DDC264C is used for low power consumption applications, and DDC264CK is used for higher speeds.

Typical features

TA +25 ° C, unless there are other instructions.

(1), for the convenience of readers, Table 1 The noise is expressed in three different units. The first part lists the noise in the units of one -millions of the full marked range; the second part represents the noise as an equivalent input charge (unit: FC); the third part converts the noise to electrons. General description DDC264's dual -switch points input channel is shown in Figure 19. DDC264 contains 64 identical input channels, which execute current to voltage points and multi -way A/D conversion functions. Each input end has two points, so the current voltage points can be carried out continuously in time. DDC264 continuously integrates input signals by switching points between the A side and the B side.

For example, when an input signal is integrated on the A side, the B -side output is digital ADC by the vehicle. This integration and A/D conversion process are controlled by the converting pin CONV. The results of the A and B side of each signal input are stored in a serial output displacement register. When the data of the displacement register is ready, the DVALID output becomes lower.

Basic integration cycle

The topology of the front end of DDC264 is an analog integrator, as shown in Figure 20. In this figure, only IN1 input is displayed. The input level consists of an operational amplifier, an optional feedback capacitor network (CF), and several switches that implement the integral cycle. The timing relationship of all switches shown in Figure 20 is shown in Figure 21. Figure 21 conceptualize the operation of the input stage of DDC264, and should not be used as a precise timing tool for design.

Fragments of reset, integration, waiting and conversion status of the DDC264 integration part are shown in Figure 22. This internal exchange network is controlled by the converter foot (CLK) and the system clock (CLK). In order to obtain the best noise performance, CONV must be synchronized with the decrease of CLK. It is recommended to perform CONV switching within the ± 10ns range of the CLK decrease.

The non -conversion input of the integralor is connected to the QGND pin. Therefore, the DDC264 simulation ground QGND should be as clean as possible. In FIG. 20, the feedback capacitor (CF) is displayed in parallel between the inverse input and output of the computing amplifier. At the beginning of the conversion, settings SA/D, Sinta, Sintb, SREF1, SREF2 and Sreset (see Figure 21).

When the A/D conversion is completed, the charge integral capacitor (CF) resets SREF1 and SRESET (see Figure 21 and Figure 22A).This process is completed during resetting. In this way, the selected capacitor is charged to the reference voltage VREF. Once the integrated capacitor is charged, SREF and Sreset are switched so that VREF will no longer be connected to the amplifier circuit when waiting for starting points (see Figure 22B). As CONV rises, Sinta is closed, and the A side begins to integrate. This process places the integration phase in its integrated mode (see Figure 22C).

The charge from the input signal was collected on the integrated capacitor, causing the voltage output of the amplifier to decrease. The decrease of CONV stops points by switching the input signal from the A side to the B side (Sinta and Sintb) to stop the integral. Before the CONV drops, the signal of the B side is converted by the A/D converter and reset it during the A side. As the inverter decreases, the B side starts to integrate the input signal. At this time, the output voltage of the A -side amplifier is provided to the input terminal of the A/D converter (see Figure 22D).

Special static discharge (ESD) structural protection input, but does not increase the current leakage of the input pins.

Integrated capacitor

In DDC264, there are four different capacitors configuration on both sides of each channel. These internal capacitors are fine -tuned in production to achieve the schedule of the ddc264 schedule. The range control position (quantifier [1: 0]) sets the values of all capacitors. Therefore, all inputs have the same full marking range as both sides of each input. Table 2 shows the capacitance value selected by each range.

Voltage benchmark

External reference voltage is used to reset the integral capacitor before the start of the integral cycle. When the A/D converter measures the voltage stored on the integral period after the integration cycle is over, it is also used by the A/D converter. During this sampling process, the external benchmark must provide the charge required by the A/D converter. For 333 μS points, the charge was converted to an average VREF current of about 825 μA. The amount of charge required for the A/D converter has nothing to do with the integration time; therefore, increasing the points will reduce the average current. For example, the 800μS scores reduce the average VREF current to 340 μA.

In different operating modes, VREF must be stable (see Figure 22). The A/D converter measured the voltage of the VREF on the integralizer. Because the integrator capacitor was originally reset to VREF at first, when the capacitor reset to the converter measuring the integral output, any reduction of VREF will be introduced. It is also important that VREF has remained stable for a long time because the change of VREF directly corresponds to changes in the full marking range. Finally, VREF should introduce as little additional noise as possible.

For these reasons, it is strongly recommended to use operationsThe amplifier buffer the external reference source, as shown in Figure 23. In this circuit, the reference voltage is generated by the+4.096V reference voltage. Low -pass filter is used to reduce noise and connect the benchmark to the operational amplifier configured to the buffer. The amplifier should have a low noise and the range of input/output co -mode that supports VREF. Although the circuit in FIG. 23 may appear unstable due to the large output capacity, it works well for OPA350. It is not recommended to place series resistors in the output lead to improve stability, because this will cause VREF to decline, which will cause a large offset.

The frequency response

The frequency response of the DDC264 is set by the front -end staker, which is the frequency response of the traditional concession. As shown in Figure 24. By adjusting the point time T int, users can change the position of 3DB bandwidth and the gap in response. The frequency response of the A/D converter of the front -end points is not important, because the converter collects the signal from the integrator. In other words, the input of the A/D converter always has a DC signal. Sample the output of the front -end integror; therefore, mixing may occur. Whenever the frequency of the input signal exceeds half of the sampling rate, the signal will be folded back to a lower frequency.

Digital interface

DDC264 digital interface passes the data clock (DCLK), effective data pins (DVALID), serial data output pins ( DOUT) and serial data input pins (DIN) synchronous serial interfaces send numbers results. The integration and conversion process is basically independent of the data retrieval process. Therefore, the frequency of CLK and DCLK does not have to be the same. Although in order to obtain the best performance, it is strongly recommended that they come from the same clock source to keep the phase relationship constant. DIN is used only at multiple converter levels, otherwise it should be connected to DGND. According to TINT, CLK, and DCLK, multiple converters can be used for chrysanthemum chain. This option greatly simplifies the application and routing of the digital output requires a large number of converters. The configuration of DDC264 is set by a dedicated register, which uses DIN U CFG and CLK U CFG pin to address.

System and Data Clock (CLK and DCLK)

The system clock is provided to CLK, and the data clock is provided to DCLK. It is recommended that the CLK pin driven by the free clock source (that is, do not start and stop CLK between conversion). Make sure the clock signal is clean to avoid over pumping or ringing. In order to get the best performance, two clocks are generated from the same clock source. After the data is moved, DCLK is disabled by lowering it when Conv conversion.

When using multiple DDC264, please pay close attention to the DCLK distribution on the printing circuit board (PCB). In particular, make sure that the deviation in the DCLK signal should be reduced as much as possible, because this may be guidedCreate the timing conflict in serial interface specifications. For more information, see multiple converters at the level.

Valid data (dvalid)

Data valid signal indicates that the data is ready. Data retrieval may begin after DVALID lower. This signal is generated using an internal clock separated from the system clock CLK. The phase relationship between the internal clock and the clock cycle is set at the first power -on and random. Because users must synchronize CONV and CLK, the DVALID signal has a random phase relationship with CONV, and the uncertainty is ± 1/FCLK. Voting DVALID eliminates any concerns about this relationship. If the data return is regular from CONV, make sure the time you need.

Reset

DDC264 by setting the reset input to low -value asynchronous resetting, as shown in Figure 25. Ensure that the interpretation pulse is at least trst width. This is very important. The reset is no failure to avoid unintentional reset. After that, the configuration register must be programmed immediately. After programming DDC264, wait at least four times before using data.

Time Example

FIG. 26 shows several integrated cycles starting after device power power, reset and configuration register programming. The top signal is CONV, provided by the user. Integrated status tracking indicates which party is integrated. As described in the data table, when the data is ready to retrieve from the DDC264, DVALID becomes a low level. It keeps keeping at a low level until the user sets DCLK to high and then returns to the low position. The text below the DVALID pulse indicates the data side available for read. The arrow is used to match the data with the corresponding integration. Table 3 shows the timing specifications of FIG. 26.

Points

The minimum color depends on the equipment used. The minimum is proportional to the frequency of the internal clock. For DDC264C with an internal clock frequency of 5MHz, the minimum time is 320 μs; for DDC264C with an internal clock frequency of 10MHz, the minimum time is 166 μs. If the minimum points are violated, DDC264 will stop continuous points for input signals. To restore normal operations (that is, continuous points) after violating the minimum tone specification, please perform three points, and last at least 5,000 internal clock cycles. In other words, when the internal clock frequency of 5MHz is used, at least 1ms each time is performed for three points. During this period, ignore DVALID PIN. After three integrations are completed, normal continuous operations can be restored and data can be retrieved.

Data format

Serial output data provided in the form of offset binary code, as shown in Table 4. Configure the format position selection in the registerThe number of bits used in the output word. When format 1, use 20 bits. When Format 0, the low level is cut off, so only 16 bits are used. Note that when Format 0, the size of LSB is 16 times the original. The output contains a offset to allow a slightly negative input from the limit reading (e.g., input from the board leak). This offset is about 0.4%of the standard.

Data retrieval

The last conversion data can be retrieved at the decrease of DVALID (see Figures 27 and Table 5). Data moves outward in the data clock DCLK.

Make sure not to retrieve the data related to changes in CONV, because this change may introduce noise. Stop before or after Conv transition, DCLK's activity is at least 2 μs.

Set the format BIT 0 (16 -bit output word) to reduce the time required for retrieval data, because there are fewer points to be removed. This technology can be used for multi -channel systems with only 16 -bit resolution.

(1), the maximum load is a DDC264 (typical 4PF), and the additional load is 5PF.

Multiple converters in the class

You can connect multiple DDC264 devices in the serial configuration; see Figure 28.

DOUT can be used with DIN, with multiple DDC264 devices with chrysanthemum chain to reduce wiring. In this operation mode, the serial data output is shifted through multiple DDC264; see Figure 28.

FIG. 29 shows the timing diagram when DIN input is used in several devices for chrysanthemum chains. Table 6 gives the timing specification of data retrieval using DIN.

Before the conversion,

Data retrieval should be performed before CONV switch. The data retrieval starts quickly after the DVALID becomes low, and it ends before Conv switching, as shown in Figure 30. In order to obtain the best performance, the data retrieval must stop TSDCV before Conv switch. This method is most suitable for longer points. The longest time that can be used for reflection is (Tint -TCMDR -TSDCV). The maximum quantity of DDC264 that can be connected by the chrysanthemum chain (format 1) is calculated:

Note: (16 × 64) τdCLK is used for format 0 Among them, cDCLK is the cycle of the data clock. For example, if TINT 1000μs and DCLK 20MHz, the maximum number of DDC264 with a format of 1 is as shown in the formula 2:

(or 14 ddc264s format 0)

After converting the switch Ending before preparing, you can get more time. Data retrieval must wait for TSDCV to start after CONV switching. For examples of this timing, see Figure 31. The longest time that can be used for retrieval is TDR - (TSDCV+Thddodv), which has nothing to do with color tone. The maximum number of DDC264 that can be connected by the chrysanthemum chain (format 1) is calculated by the formula 3:

Note: (16 × 64) τdcLk indicates the format 0.

For DCLK 20MHz, the maximum number of DDC264 is 4 (for format 0, then 5).

Review switching before and after conversion

For the absolute maximum time of data retrieval, data switching can be retrieved before and after Conv. Almost all color tones can be used for data retrieval. FIG. 32 illustrates how to complete this process by combining the first two methods. As mentioned earlier, it is suspended to prevent digital noise during the conversion and switching period, and it is completed before the next data preparation is ready. The maximum number of DDC264 that can be connected by the chrysanthemum chain is:

Note: (16 × 64) τDCLK is used for format 0.

For Tint 400 μs and DCLK 20MHz, the maximum number of DDC264S is 6 (for format 0, then 7).

Configuration register

Reading and writing operation

The configuration register must be programmed after power -on or equipment reset. DIN_CFG, CLK_CFG, and RESET pins are used to write to the register. When starting the operation, keep the Conv Low and the selection reset; see Figure 33. Then start transferring the configuration data on DIN_The configuration data to write the highest effective position of the configuration register. Data is dropped by CLK_CFG internal locks. Do not allow the configuration register to be partially written. Make sure to send all 16 bits when updating the register.

The optional reading of the configuration register can be used in order after writing. Reading during the period, 320 u0026#39; 0 u0026#39; s, and then the 16 -bit configuration data moves with 4 digits and the check mode on the DOUT pin of DCLK to the edge of DCLK. Check mode can be used to check or verify the DOUT function.

Note: When format 1, the verification mode is 300, only the last 72 -bit non -zero. For each DDC264, this output sequence is repeated twice, and the configuration is read backSupport chrysanthemum chain. Table 8 shows the configuration of the check mode during the reading period. Table 9 shows the timing of the configuration register read and write operation. Selected transformers started to run normally.

Layout

Power and ground

AVDD and DVD should be as quiet as possible. It is particularly important to eliminate AVDD noise that is not synchronized with DDC264 operations. Figure 34 illustrates how to power DDC264. Each DDC264 has an internal bypass container on AVDD and DVD; therefore, the only external bypass electrical container that is usually needed is 10 μF ceramic capacitors, each PCB. It is recommended to connect simulation and digital grounding (agng and dgnd) to a single ground plane on PCB.

Shielding analog signal channel Like any precision circuit, the carefully PCB layout ensures the best performance. Short -distance direct interconnection must be performed to avoid bruises, especially at the simulation input pin and QGND. The simulation input pin has high impedance and is extremely sensitive to external noise. QGND pin should be considered as a sensitive simulation signal and directly connected to the power ground through appropriate shielding. If not shielded, the leakage current between the PCB line may exceed the input bias current of DDC264. The digital signal should be as far away from the analog input signal on the PCB.

Power -powered order

Before the device is powered on, all numbers and simulation inputs must be low. When power -on, all these signals should be kept at a lower level until the power supply is stable, as shown in Figure 35. The simulation power supply must be started before or at the same time before or at the same time. At this time, start to provide the main clock signal to the CLK pin. Wait time T or, and then give the residence pulse. After the reset is released, the configuration register must be written. Table 11 shows the timing of the power sequence.