In order to further increase the 3D integration density, the solution proposed by the American semiconductor academia is to use carbon nanotube technology (represented by Stanford Huang Hansen, Subhasish Mitra and MIT Max Shulaker). At present, the American semiconductor academia is determined to commercialize carbon nanotubes and N3XT-related technologies, and good results have been achieved so far.

As Moore's Law gradually enters a plateau, the performance improvement of semiconductor chips is increasingly dependent on the improvement of chip architecture design and advanced packaging technology, rather than the decline in the physical size of the semiconductor process. On the other hand, with the advent of the era of artificial intelligence, more and more computing chip designs need to consider the computing power requirements of artificial intelligence. Therefore, how to design and optimize the related AN5275 chip architecture, technology and packaging system for artificial intelligence applications in the next decade has become a very concerned issue in academia and industry.

At the 2021 International Electronic Devices Conference (IEDM2021) held last week, we saw a lot of related research published, including a paper from MIT and Stanford University entitled "The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup , Co-Design" ("The Computing-Oriented Future Hardware Platform: N3XT 3D MOSAIC and Illusion Scaleup Collaborative Design"). This research is not a day's work, but the latest research results of the American Semiconductor Technology Academic Research School represented by MIT and Stanford University in the field of ultra-high-density 3D integration over the years, and also plans a future roadmap.

At present, although the 3D integration technology represented by TSV has matured, the spacing between 3D integrated vias is still very large, in the order of 10um. In order to further increase the 3D integration density, the solution proposed by the American semiconductor academia is to use carbon nanotube technology (represented by Stanford Huang Hansen, Subhasish Mitra and MIT Max Shulaker). An important advantage of carbon nanotube technology is that ultra-high density 3D stacked vias can be realized, and the via pitch can be reduced to 100nm, which is two orders of magnitude smaller than the current TSV via pitch. At the same time, considering the current artificial intelligence application, its main performance bottleneck lies in memory access, because the neural network model required by artificial intelligence requires a lot of memory resources at runtime, so it is necessary to integrate memory and computing logic in a very high efficiency Together. The combination of the two is to use carbon nanotube technology and ultra-high-density 3D integration to integrate computing with (new) memory, and the solution proposed by the American semiconductor community is based on the full name of nanoengineering. Specifically, N3XT uses different computing processes to achieve multiple integration technologies, including traditional carbon nanotube technology.

Using the N3XT as a unit, multiple different N3XT units (and legacy chips) can be further integrated in various forms. For example, multiple N3XT units can be stacked together in the form of TSVs, and multiple N3XTs can be packaged on a silicon substrate in the form of 2.5D packages, enabling ultra-large-scale heterogeneous integration. This scheme of integrating various chips in various ways is called MOSAIC (ie Monolithc/stacked/assembledIC).

So far, the main process and device technology of this study (i.e. N3XT3DMOSAIC in the title of the paper) has appeared before us. The next step is how to maximize the efficiency of this large-scale integration at the system level.

Optimized ultra-high-density 3D integrated mating system to improve performance by a thousand times

With the increasing demand for computing power of artificial intelligence, future N3XT systems also need to consider how to optimize at the system level to meet the computing power requirements of artificial intelligence; in other words, if given 100 N3XT systems, how Optimizing tasks to make overall computing the most efficient? If this problem can be solved well, the N3XT system can handle the scale of artificial intelligence computing problems well.

In this regard, the researchers propose the solution of IllusionScaleup. IllusionScaleup mainly targets deep learning algorithms in artificial intelligence applications. In the system design approach, the entire neural network is first divided into multiple parts, and part of the computing tasks are assigned to each N3XT module. For example, segmentation can be in units of neural network layers. When the computational load of one layer is relatively small, multiple layers of computation can be distributed on a single N3XT module; when the computational load of one layer is large, a layer of network can also be divided into multiple parts and assigned to different N3XT modules. Due to the serial computation relationship between the different layers of the neural network, different N3XT modules can be pipelined. In addition, since each N3XT is only responsible for one layer of computation, it can ensure that the weights of the neural network do not need to move between modules, but only the intermediate results, which greatly reduces the extra cost of data movement.

Finally, since the N3XT system can use next-generation non-volatile memory such as RRAM, it can support fast switching. To this end, the authors also propose that this can be turned off without the N3XT unit without the use of the N3XT unit. a feature, which greatly saves leakage current. By using this strategy, the performance of each N3XT (such as increasing the number of stacked layers of N3XT and the interconnection bandwidth between N3XTs) can be linearly increased to meet the exponentially increasing computing power of artificial intelligence computing computing power. Using this approach, studies have shown that the performance of the entire N3XT3DMOSAIC can be improved by a factor of 100-1000 over current 3D stacking.

Ultra-high-density 3D integrated commercialization road

At present, the American semiconductor academia is determined to commercialize carbon nanotubes and N3XT-related technologies, and good results have been achieved so far. In general, the commercialization of carbon nanotubes in the United States includes many parties: the US government research agency DARPA, the universities MIT and Stanford University, and the US OEMSkyWater, which specializes in advanced semiconductor technology OEMs. Years ago, DARPA heavily funded research into next-generation semiconductor technologies related to carbon nanotubes. Two years ago, MIT Max Shulake led the research team to realize the first carbon nanotube and RRAM 3D stacked chip wafer at SkyWater. Over the past two years, the same team has accomplished many milestones, including the first carbon nanotube-implemented VLSI (RISC-V processor), the first carbon nanotube PDK, and more. At the same time, Stanford University professor Hansen Huang himself served as the vice president of TSMC during the 2018-2020 academic sabbatical. After returning to Stanford University, he will still serve as the chief scientist and believes that he will become the chief scientist of carbon nanotube ultra-high density. the scientist.

On the other hand, in the semiconductor industry, the pursuit of large-scale high-density 3D packaging is also visible. For example, AMD's 3DV-Cache released earlier this year uses TSMC's latest SoIC technology, which can reduce the 3D stacking via pitch to the order of 1um, thereby greatly improving the interconnect density of 3D stacking. This year, Intel also announced PonteVechio, in what it says is its most ambitious chip plan yet. Ultra-large-scale 2.5D and 3D interconnects and packaging are achieved with TSV and Intel's unique EMIB technology. The semiconductor industry has a strong demand for next-generation ultra-high-density packaging and interconnection to meet the needs of artificial intelligence high-performance computing. In this case, we believe that N3XT3DMOSAIC gives an evolutionary roadmap for future related technologies from an academic point of view, and at least some of them (such as 3DMOSAIC) will be put into commercial use in the next few years. With more research and verification, carbon nanomaterials Tube technology is expected to officially enter the business in a slightly distant time.

In China, related carbon nanotube technology also has a good accumulation of research in academia. Academician Peng of Peking University and other teams have also published very influential research results in the world's top journals. Ultra-large-scale high-density 3D integration is a systematic project that requires coordinated development of semiconductor technology and equipment, advanced packaging technology and circuit architecture. We hope that China's related technologies can truly expand from the current single-point breakthrough of carbon nanotube equipment to system breakthroughs, and at the same time With the development of the semiconductor OEM and packaging industry, there can be enough technology accumulation to lead the development of the whole technology trend in the next generation of the new paradigm of semiconductor based on the new generation of equipment and packaging technology.