Features

High -efficiency power level (up to 97%), low RDS (on) MOSFET (TJ 25 ° C is 80 m )

working power supply voltage up to 50 V (maximum absolute value 70 A)

DRV8312 (power attenuation): up to 3.5-A continuous phase current (peak 6.5---- A)

DRV8332 (power pad): up to 8-a continuous phase current (peak 13-a)

123] PWM operating frequency is as high as 500 kHz

Integrated self -protection circuit, including under pressure, overheating, overload and short circuit

Stream protection

Independent power supply and grounding pin of each half -bridge

smart door driver and anti -crossing conduction

No external buffer or Schottky diode

Application

Brushless DC motor

Three -phase permanent magnet synchronous motor

inverter

half -bridge drive

Robot control system

3 Instructions

DRV83X2 is a high -performance integrated three -phase motor drive with an advanced protection system.

Due to the low RDS (ON) and smart door driver design of the power MOSFET, the efficiency of these motor drivers can reach 97%. This high -efficiency uses smaller power and heat dissipation films, and these devices are good candidates for energy -saving applications.

DRV83X2 requires two power supply, one for GVDD and VDD, and the other is up to 50V for PVDD. DRV83X2 can work at the frequency of up to 500 kg, while still maintaining accurate control and efficiency. These devices also have an innovative protection system, and the protection equipment is exempted from the effects of various failure conditions that may damage the system. These protection measures include short -circuit protection, over -current protection, under pressure protection, and two -level heat protection. DRV83X2 has a current -limiting circuit that prevents the device from being stopped during the load transient (such as motor startup). Programmable over -current detector allows adjustable current limits and protection levels to meet different motor requirements.

DRV83X2 has a unique independent power supply and ground pins per semi -bridge. These pins make it provides current measurement through external parallel resistorsPossibly and support half -bridge drives with different power supply voltage requirements.

Equipment information

(1), please refer to the appointment appendix at the end of the data table.

Simplified application diagrams

Typical features

Detailed description Overview

When the three high impedance diode were reset, the high -impedance current passed through three high -resistance diode. When the RESET AU A is high and PWM U A is low, the OUT U A is driven low, and its low -side FET is enabled. When the RESET AU A is high and PWM U A is high, the OUT U A is driven high, and its high side FET is enabled. The same is true of B and C.

Figure Figure

Feature description

Error report

The failure and OTW pin are low -electric open roads. Discost output. Their function is to send protection mode signals to PWM controller or other system control devices.

Any failure that causes the device to turn off, such as overheating, over -current shutdown, or under pressure protection, will send a signal from the fault pins. Similarly, when the component temperature exceeds 125 ° C, OTW becomes lower (see Table 1).

TI recommends using the system microcontroller to monitor the OTW signal, and responds to the OTW signal by reducing the load current to prevent the device from further heating and the device overheating (OTSD).

It becomes a red UCE external component count, providing an internal pull resistor that connects to the internal VREG (3.3V) on the fault and OTW output terminal. The level compliance of 5V logic can be obtained by adding the external pull -up resistor to 5V (more specifications, please refer to the electrical characteristics of the data table).

Device protection system

DRV83X2 contains advanced protection circuits. After careful design, it helps system integration and ease of use, and protective equipment does not due Permanent faults occur in many failure conditions. DRV83X2 immediately sets the semi-bridge output to high impedance (Hi-Z) state and asserted that the failure of the fault is low, thereby responding to the failure. In the case of overcurrent or overheating, when the fault conditions are eliminated or the voltage of the gate power supply is increased, the device is automatically recovered. In order to obtain as high reliability as possible, when the current shutdown (OCSD) or OTSD failure recovers, the external reset device is reset within 1 second after shutdown.

Self -lifting capacitors under pressure protection

Being a deviceWhen running at a lower switching frequency (for example, a 100 NF self -raising capacitor is less than 10 kHz), the self -raising capacitor voltage may not be able to maintain a proper voltage level for the high -voltage side grid drive. Self -lifting capacitors owed pressure protection circuit (BST_VP) can prevent potential failures of high -voltage MOSFETs. When the voltage on the self -lifting capacitor is lower than the values required for safe operation, the DRV83X2 will start the self -raising capacitor charging order (a short time off the high -voltage side field effect transistor), until the capacitor raised the capacitor to correctly charge the safe operation. When the PWM occupation ratio is too high (for example, when 10 kHz, the closing time is less than 20 ns), this function can also be activated. Please note that if the output end of the output terminal during the BST_UVP operation may not be charged by the self -lifting capacitor. Therefore, it is recommended to turn on the low -voltage side FET at least 50ns in each PWM cycle to avoid BST_VP operations.

For applications that are lower than 10 kHz and do not trigger BST_-UVP protection, larger self-raising capacitors (e.g., 1-UF capacitor for 800 Hz operations). When using a self -raising capacitor greater than 220 NF, it is recommended to add 5 ohm resistors between the 12V GVDD power supply and the GVDD U X pins to limit the influx of the internal guidance of the diode.

Over -current (OC) Protection

DRV83X2 has an independent rapid response current detector, and has a programmable check -up threshold (OC threshold) on all high and low -side power grades. There are two OC protection settings through mode selection pins: cycle cycle (CBC) flow limit mode and OC atresia (OCL) shutdown mode.

In the CBC flow limit mode, the detector output is monitored by two protection systems. The first protection system controls the power level to prevent the output current from further increased, that is, it executes the CBC flow limit function instead of turning the device prematurely. This feature can effectively limit the flow of motor startup or during the transient process without damaging the device. In the case of short-circuit of power supply and short-circuit of ground, because the current limiting circuit may not be able to control the current to the appropriate level, the second protection system triggers the atresia and close, resulting in the relevant semi-bridge being set to high impedance (Hi-Z) state state state Essence Restrictions and overcurrent protection are independent of semi -bridge A, B and C, respectively.

FIG. 6 illustrates the circulation operation under the high -sides OC event, and Figure 7 shows the circular operation of the low -side OC. The dotted line is the operation waveform of the non -trigger the CBC event, and the solid line is the waveform of the CBC event. In the CBC flow limit mode, when the low -side FET OC is detected, the device will close the affected low -side FET and keep the high side FET on the same half of the bridge until the next PWM cycle; when the high side FET detects the high side FET, the high side FET is detected. When OC, the device will close the affected high -side FET and open the low side FET on the half bridge until the next PWM cycle.

ValueIt should be noted that if the current event occurs in the CBC, the input of the half-bridge remains the constant value, and at the end of the overcurrent event, the relevant half bridge will be in HI-Z. The circulating input will allow the output to continue to run normally.

Under the OC atresia closing mode, the CBC current limit and error recovery circuit are disabled, and the over -current situation will cause the device to turn off. After shutting down, you must assert that reset_a, reset_b and reset_c to restore normal operation after eliminating the current conditions.

In order to increase flexibility, the OC threshold can be programmed by a single external resistor connected between the OC_ADJ pins and the AgND pins. For information about the correlation between programming resistance and OC threshold, see Table 2.

The value in Table 2 shows the typical OC threshold of the given resistor. Assuming that the resistance on the OC_ADJ pins of multiple devices is fixed, the changes between the device in the OC threshold measurement may be 20%. Therefore, this function design is used for system protection, not for accurate current control.

It should be noted that a normal -working over -current detector assumes that there is a suitable inductor or power iron oxygen magnetic bead at the power level output side. Short -circuit protection cannot be guaranteed through the direct short circuit of the power -level output pins.

Over -temperature protection

DRV83X2 has a two -stage temperature protection system. When the device knot temperature exceeds 125 ° C (nominal value), the device will send a activated low alarm signal (OTW ); If the installation temperature exceeds 150 ° C (nominal value), the device will enter the hot stack state, causing all semi-bridge output to be set to high impedance (Hi-Z) state, and the fault is assertive to be low. In this case, OTSD is locked, and RESET_A, Reset_b and Reset_c must be asserted to be low to remove the lock.

UVP and POR circuits of the underwriting (UVP) and the power -on reset (POR)

DRV83X2 fully protect the equipment under any power -powered/disconnection and power failure. At the time of power, the POR circuit is reset to the current circuit and ensures that when the voltage of the GVDD U X and VDD power supply reaches 9.8 V (typical values), all circuits can be fully working. Although GVDD U X and VDD are monitored independently, any VDD or GVDD_X pins below the UVP threshold drop will cause all semi-bridge output to be immediately set to high impedance (Hi-Z) state. Essence When all the power supply voltage on the capacitor is higher than the UVP threshold, the device will automatically resume operation.

Device reset

provides three reset pins for independent control for half bridge A, B, and C. When the RESET UX is asserted to be low, the two power grade FETs in the Bridge X are forcibly entered into high impedance (Hi-z) Status.

The transition allowed device on the input of the reset input to resume operation after the shutdown failure. In other words, when the half -bridge X is closed in the CBC mode, the low to high conversion of the RESET UX pins will clear the fault and fault pins. When OTSD or OC is closed under the lock mode, all three reset ""A"