A complete interface between LNB

I2CTM bus

Built -in DC/DC controller

Single 12V power operation

Exactly built -in 22kHz sound tone

oscillator

In line with the widely accepted standard

The fast oscillator starts

diseqctm encoding

Built -in 22kHz sound tunnel

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Support two -way DiseqCTM

From machine circulation function

Operation

LNB short circuit protection and diagnosis

Cable length digital compensation

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123] Excessive internal temperature protection

ESD rated value 4KV power power

Input output pins

Explanation

Used to simulate and digital satellite set -top box 21 units TV/satellite TV card single-chip pressure regulator and interface IC, assembled in SO-20 and Powerso-20, is specifically designed to provide power supply and LNB 13/18V, 22kHz audio signal antenna or multi-function switch Under the inverter box. In this application field, it provides a simple I2CTM standard interface with a complete solution power consumption with a complete ingredient count. This integrated circuit has a built -in DC/DC boost controller from 8 to 15V, and the generated voltage rear regulator work at a minimum dissipation power. The IOU locking circuit will be provided as the VCC provided below the fixed threshold (usually 6.7V). This internal 22kHz audio generator is aimed at the factory in accordance with the standard, and can be performed by the I2CTM interface or special pins (dsqin), allowing Diseqctm data encoding (*) immediately. All functions of this integrated circuit The position (SR, 8 bits) on the 6 system register through the I2CTM bus. This same register can be read back, and the two places will report the diagnosis state. When the integrated circuit is put in the standby (EN bits are low), the power block is disabled and circulated to switch LT1 and LT2 pin closure, so all LNB main control power supply and control function receiver (**) is left. When the regulator block activation (EN is high), the output can be the logical control to 13 or 18 V (typical values), and the non -disease LNB by the VSEL bit (voltage selection) for remote control. In addition, this is possible to add 1V (typical values) to compensate for the selected voltage by 1V (typical values). In order to minimize the power consumption and reduce the internal voltage of the output voltage adjustment converter to make the linear regulator at least work dropout. Another part of SR is for remote control non -Diseqc LNBS: 10 (tone enable) bit. When it is set to high, A no matter what, it will produce a continuous 22kHz tone dsqin pinsCircuit. Ten digits must be used as DISEQCTM encoding. The completely two -way DiseqCTM interface is built -in 22kHz tone detector. Its input pin (Detin) must be coupled to the Diseqctm bus, and the extracted PWK data can be available at DSQOUT pin (*). In order to improve the design of the design of the new LNB remote control, the simulation modulation input pin is available (EXTM). Proper DC atresia must use a capacitor coupling modulation signal source to the EXTM pin. When the external modulation is not used, the relevant pins can be left.

The current limit block has two thresholds that can be selected by the ISEL bit of SR, between 400 and 550mA (ISEL height), and the higher threshold is between 500 and 650mA (ISEL ISEL Low). The current protective block is SOA type. This limits the short -circuit current (ISC) at 200 mAh, is ISEL height, and connects to ground when the output port is 300 mAh. You can set short -circuit current static protection (simple current clamp) or named after the PCL bit of SR; when PCL (pulse current limit) is set to low, overcurrent protection circuit work dynamics: Once the overload is detected, the output is usually closed for a period of 900. millisecond. At the same time, the OLF bit register of the system is set to high. After this period of time, the output recovers for a period of time T 1/10TOFF (typical value). If the overload is still detected, the protective circuit will be circulated again through Toff and Dun. If the overload is not detected at the end of the whole ton, the normal operation is restored, and the OLF bit is reset to a low. The typical TON+TOFF time is 990ms, which is fixed in the internal timer. This dynamic operation can greatly reduce the power consumption during short circuits, and still ensure that good power -on startup is in most cases (**). However, in some cases, the high -capacitance load of the output end may cause dynamic protection to start difficulty. This can be set up by starting any force to start starting (PCL high) in static mode, and then switch to a certain time of dynamic mode (PCL low). When in the static mode, when the current is clamp, the OLF bit is high as the overload condition is cleared. The IC can also prevent overheating: when the knot temperature exceeds 150 ° C (typical), the booster converter and the linear regulator are turned off, the loop slot switch is turned on, and the OTF bit of the SR is set to high. Return to normal operations, OTF bits are cooled to 140 ° C (typical values).

(1): External components need to meet the hardware requirements of the two -way DiseqCTM bus. Using this IC does not mean that the entire application fully complies with DiseqCTM specifications.

(2): There is no effect on the flow -limiting circuit on the ring switch. When EN is low, the current flowing from LT1 to LT2 must be subject to external restrictions.

(1) Set GND

(2) Filter according to the EUTELSAT's recommended filter to implement DiseqCTM 2.x. 123]

(3) IC2 is ST FETTKY, STS4DNFS30L, including the Schottky diode and N-channel MOS FET required by the DC/DC converter, in a SO-8 package. You can use the Schutki diode (STPS2L3A or similar product) and N -channel MOS FET (STN4NF03L or similar product) instead of

I2C bus interface

from main μP to LNBP21 [123

] Data transmission Viceversa has a bus interface through two wires I2C, which must be connected from two line SDAs and upper -pull resistors to the positive power supply voltage).

Data validity

As shown in Figure 1, the data on the SDA line must be stable at the clock high time. The level of the data cable can only be the low clock signal on the SCL line. The start and stop condition is shown in Figure 2. The starting condition is the low transition of the SDA cable when the SCL is high. The stop condition is the SDA cable when the SCL is high. The conditions must be sent before each start.

byte format

Each byte transmitted to the SDA must contain 8 bits. You must follow an AC knowledge after each byte. First transmit MSB. Acknowledge the SDA cable of the main (μP) during the confirmation of the clock pulse (see Figure 3). The recognition of the peripheral device (LNBP21) must lower the SDA line during this clock pulse during the clock pulse, and the SDA cable must be a stable low level. The addressable peripheral equipment must receive each byte, and in another case, the SDA row is maintained at a high level in the ninth clock pulse time. In this case, the main transmitter can generate stop information to stop transmission. LNBP21 does not generate confirmation, if the VCC power supply is lower than the lack of the underwriting lock (6.7V typical value). Without response transmission, avoid detecting LNBP21, μP can use simpler transmission: it only needs to wait for one clock without checking SLAVE confirmation and sending new data. Of course, this method is not very protected and misunderstood, reducing the antidity.

LNBP1 Software Description

Interface protocol

The interface protocol includes: -Bactive conditions-chip address byte byte bytes hexadecimal 10th inlet 10. /11 (LSB bit determination ( 1)/write ( 0) transmission) -Data sequence (1 byte+confirmation) -Stop condition (p)

[ 123] ACK Confirm

s Start

P Stop

r/w reading/writing

r, w reading and writing bit

r Reading only

All bits are reset to 0

Transmission data (I2C bus writing mode). When the R/W bit in the chip address is set to 0, the main μP can be available. Write the system register (SR) through the I2C bus. Only 6 available 8 can be written by μP, because maintenance 2 retains diagnostic signs and is read only.

Receive data (I2C bus reading mode)

lnbp21 can provide the host with the system through the I2C bus registration information in the read mode. Reading mode is activated by the Lord by sending a chip address set to 1 by sending R/W bits. LNBP21 at the clock position generated by the following host sent a byte (transmitted MSB first) on the SDA data bus. In the ninth clock, the MCU host can:-start to confirm the receiving another byte from LNBP21 in this way;

-The response, stop reading mode communication. When the entire register is read back by μP, only two OLF and OTF read only the unknown information about LNBP21.

Unless there are other regulations, the value is a typical value

Electric I2C interface reset

LNBP21 built -in I2C interface is automatic boot automatic boot automatic Rebate. As long as the VCC keeps the low voltage lock threshold (6.7V typical value), the interface will not respond to any I2C command and system register (SR) to be initialized to all zero, so the power block is disabled. Once the VCC rises to 7.3V, I2C interface starts to work, and SR can be configured by the main μP. This is due to providing about 500 millivol to lag in UVL to avoid errors to avoid re -triggered threshold -to -turn on -electric reset circuits. DiseqCTM implements LNBP21 to help system designers realize two -way (2.x) DiseqC protocol through simple PWK modulation/22kHz carrier demodulation. PWK data is used in LNBP21 and main μP with 3.3 and 5V MI remote controls. This data is exchanged through two special pins, in order to keep PWK data accurate with PWK modulation as much as possible. These two pins should be directly connected to the two I/O pins that are connected to μP, so the mission PWK data that is left to the resident firmware coding and decoding is in line with the Diseqc solution. The system is fully complied with specifications. Therefore, using only LNBP21 does not mean. System designers should also consider bus hardware requirements, including the transmitter measured at 22kHz at 22kHz. Restricted at the frequency attenuation of Karilel. This impedance must be 15 ohm at 22kHz, and it is reduced to 0 ohm at DC to allow the power flow to the peripheral equipment. This can be simply connected through the LR endLNBP, as the typical application circuit is shown in page 5. Unidirectional (1.x) Diseqc and non -Diseqc systems usually do not need this termination, and the OUT pin can be directly connected to the power port of the LNB regulator. It is not necessary to avoid electromagnetic interference with Detin and DSQOUT pins. The address Pin connects this pin to the chip I2C interface address is 0001000, but you can choose to set 4 fixed voltage grades pins in 4 different addresses (see Table 10 on the first page).

The electrical characteristics of the lnbp series (TJ 0 to 85 ° C, EN 1, LLC 0, TEN 0, ISEL 0, PCL 0, dsqin 0, vin 12V, IOUT 50mA, unless there are other regulations. Please refer to the software instructions for the I2C access system register)

Mental and sensing electrical characteristics (TJ 0 to 85 ° C, vin 12V)

Typical features (unless there are other regulations, TJ 25 ° C)

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123] Terminal design description

During the normal operation, the device will dissipate some strength. Under the maximum rated output current (500mA), the voltage drop on the linear regulator causes the total energy consumption of about 1.7W. The heat generated by the heat dissipation sheet is required to keep the knot temperature below the ultra -temperature protection threshold. Assuming that the internal temperature is 40 ° C, the total Hong Kong Radio AMB must be less than 50 ° C/W. Although the connectable pilot power component is used to a small radiator or metal frame receiver, the power component installed on the surface must be limited by thermal efficiency. The easiest solution is to use the large -scale continuous copper region of the ground floor to heat dissipation IC. The IC's SO-20 package has 4 GND pins not only for electrical grounding, but also provides low-calorie silicon wafers and PCB heat sinks. Suppose RthJ-C is equal to 15 ° C/W, and the maximum temperature of PCB is 35 ° C/W heat sink. If the minimum copper area with a minimum value of 25cm2 is exactly the body below the IC. This area can be a multi -layer PCB, or the position of the GND region IC is not damaged in the opposite side of the PCB. In these two cases, the copper region between the IC GND pins and the scattered path must have low thermal resistance. In Figure 4, it shows SO-20 packaging with a double PCB, where the area of u200bu200bthe dissipated area is used for heat connection through 32 pores and filled with welded. This arrangement, L 50mm, Rth with a RTH of about 25 ° C/WC-A.Different layouts are also possible.Basically, principles are recommended to retain the IC and its grounding needles in the dissipation zone; providing as many pores as possible; designing a shaped as possible, do not interrupt other copper traces.Due to the existence of grounding below the IC, the Hong Kong and Taiwan tax rates planned by PowerSo-20 are much lower than that of SO-20, only 2 ° C/W.Therefore, the copper area must be much lower and must provide the same power and the copper area of at least 12cm2. See Figure 5.