Features

Support DSD and PCM format

24 -bit resolution

]

Simulation performance:

Dynamic range:

132 db (9 V RMS, single channel) [123) [123) ] 129 db (4.5 V RMS, stereo)

127 db (2 V RMS, stereo)

Thd+N: 0.0004%

Differential current output: 7.8 ma p-p

8 × over-sampling digital filter: -The blocking attenuation: --130 db

Passing ripple: ± 0.00001 db

Sample frequency frequency : 10 kHz to 200 kHz

System clock: 128, 192, 256, 384, 512 or 768 FS (automatic detection)

] Accept 16-bit, 20-bit and 24-bit audio data

PCM Complaint Format: Standard, I2S and Left-Equired

A optional interface of external digital filter or DSP

I2C compatible serial port

[[] [

123]

User's programmable mode control:

Digital attenuation: 0 db to –120 db, 0.5 db/step

#8722; Digital to aggravate Digital filter attenuation: Fast or Slow

Softness

[ 123] Dual power operation:

5 volt model voltage, 3.3 volt digital voltage

123]

Small 28 lead SSOP package,Lead -free product

Application

A/V receiver

SACD player

DVD player

HD TV receiver

# 8226;

Auto audio system

Digital multi -channel recorder

Audio application

Description

DSD1794 is a single -chip CMOS integrated circuit, including stereo -digital modulus converters and support circuits in a small 28 -lead SSOP package. The data converter adopts the TI's advanced segmental modulus converter structure to obtain excellent dynamic performance and improved clock jitter tolerance. DSD1794 provides a balanced current output, allowing users to optimize the simulation performance from the outside. DSD1794 accepts PCM and DSD audio data formats, and provides simple interfaces with audio DSP and decoder chips. DSD1794 also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Support the sampling rate of up to 200 kHz. You can access a full set of user programming functions through the serial port compatible with the I2C.

Function box diagram

Typical performance curve

Digital filter

Digital filter response

[123 ]

Go to aggravate the filter

Analog dynamic performance

Power voltage characteristics

Note: PCM mode, TA 25 ° C, VDD 3.3 V, the measurement circuit is shown in Figure 34 (vout 4.5 V RMS). Temperature feature

Note: PCM mode, VDD 3.3V, VCC 5V, measurement circuit is shown in Figure 34 (vout 4.5V RMS).

Note: DSD mode (FIR-4), 32768 points 8 average, TA 25 ° C, VDD 3.3V , VCC 5V, the measurement circuit is shown in Figure 35Essence System clock and reset function

System clock input

DSD1794 requires a system clock to operate digital filter and high -end DAC modulator. The system clock is applied to the SCK input terminal (pin 7). DSD1794 has a system clock detection circuit that can automatically detect the operating frequency of the system clock. Table 1 shows a system clock frequency example with common audio sampling rates. If the sampling rate of the Delta-Sigma modulator is selected as 128 FS, the system clock frequency is required to exceed 256 FS.

The clock input system is required as shown in Figure 24. In order to obtain the best performance, it is important to use low phase jitter and noise. Provide a good choice for Texas's L1794 series clock.

(1), I2C fast mode does not support the clock rate of this system.

(2), the given sampling frequency does not support the clock rate of this system.

Power -powered and external reset function

DSD1794 includes power -on reset function. FIG. 25 shows the operation of this function. When VDD GT; 2 V, the power -on reset function is enabled. The initialization sequence requires 1024 system clocks, starting from VDD GT; 2V. After the initialization cycle is over, the DSD1794 is set to its default reset state, as described in the mode control register of this data table.

DSD1794 also includes external resetting function using RST input (pin 14). This allows external controller or main resettlement circuits to forced DSD1794 to initialize to its default reset state.

FIG. 26 shows external reset operations and timing. Set the first pin to logic 0, at least 20 ns. This RST pin is then set to logic 1 state, thereby starting the initialized sequence, which requires 1024 system clock cycles. External reset is particularly useful in the application between DSD1794 power power and system clock activation.

Audio data interface

Audio serial interface

The audio interface port is a 3 -line serial port. It includes PLRCK (pin 4), PBCK (pin 6) and PDATA (pin 5). PBCK is a serial audio clock, which is used to enter the serial displacement register of the audio interface on the serial data on the PDATA. The serial data is recorded in DSD1794 rising along the PBCK. PLRCK is a serial audio left/right character clock.

DSD1794 requires PLRCK to synchronize with the system clock, but does not require a specific phase relationship between PLRCK and the system clock.

If pThe relationship between the LRCK and the system clock changes more than ± 6 pbck. The internal operation is initialized in 1/fs, and the simulation output is forced to be a bipolar zero.

PCM audio data format and timing

DSD1794 support the industry standard audio data format, including standard right alignment, I2S, and left. The data format is shown in Figure 28. Use the format position FMT [2: 0] in the control register 18 to select the data format. The default data format is 24 -bit I2S. All formats require binary binary supplementary code, MSB first audio data. Figure 27 shows the detailed sequential map of the serial audio interface.

(1), standard data format (right alignment); L-channel high, R-channel low

(2), left-to-alignment data format; L-channel high, R-channel low

(3), I2S data format; L-channel Low, R-Channel High

External digital filter interface and timing

DSD1794 supports external numbers with 3 or 4 line synchronous serial ports. Filter interface, allowing external digital filters. External filters include Texas Instruments DF1704 and DF1706, Pacific Microsonics PMD200 or programmable digital signal processors.

In the external direction mode, PLRCK (pin 4), PBCK (pin 6), and PDATA (pin 5) are defined as the word clock WDCK, Bit clock BCK, and single -channel data data. The external digital filter interface is selected by using the DFTH bit of the control register 20. The function is to bypass the internal digital filter of the DSD1794.

When the DFMS bit of the control register 19 is set, DSD1794 can process stereo data. In this case, DSDL (pin 1) and DSDR (pin 2) are defined as L channel data and R channel data input, respectively.

The detailed information of the external digital filter interface mode is provided in the application part of the external digital filter interface of this data table.

Direct streaming number (DSD) format interface and timing

DSD1794 support DSD format interface operation, including internal analog FIR filters for external noise filtering. The DSD format interface consists of a 3 -line synchronous serial port, which includes DBCK (pin 3), DSDL (pin 1), and DSDR (pin 2). DBCK is a serial clock. DSDL and DSDR are L channels andR channel DSD data input. They are recorded in DSD1794 on the edge of DBCK. PLRCK (pin 4) and PBCK (pin 6) are connected to GND in DSD mode. Activate the DSD format interface by setting the DSD bit of the control register 20.

The DSD format (DSD mode) application interface part of this data table provides detailed information about the DSD mode.

Serial control interface (I2C)

DSD1794 supports i2C series bus and standard and fast mode data transmission protocol as the device. I2C specification 2.0 explained the protocol.

The subordinate address

DSD1794 has 7 digits as your own machine address. The preset from the top five (MSB) from the machine address is 10011. The lower two digits of the address bytes are device options, which can be defined by ADR1 and ADR0 end users. The same bus can connect up to four DSD1794 at a time. Each DSD1794 responds when receiving its own camera address.

Grouping protocol

The main device must control the group protocol. The agreement consists of the starting conditions, the address, the read/writing position, the read and write data, or read the confirmation, and the stop condition. DSD1794 only supports the receiver and the transmitter.

Write to the register

The host can use a single or multiple access to any DSD1794 register. The host sends a DSD1794 from the machine address and a position, a register address and data. If you need to access multiple times, the address is the address of the start register, and the data to be transmitted later. When the data is received correctly, the index register is automatically increased by 1. When the index register reaches 0x7F, the next value is 0x0. When visiting an unfarished register, DSD1794 does not send confirmation. Write a operation drawing in Figure 30.

Reading the register

The host can read the DSD1794 register. The value of the register address is first stored in the indirect index register. The host sends a read -a bit DSD1794 from the machine address after the storage register address. Then DSD1794 transmits the data pointed by the index register. When the data is transmitted during multiple access periods, the index register is automatically increased by 1. (When you first enter the reading mode after writing, the index register will not increase. When the index register reaches 0x7F, the next value is 0x0. When the index register is 0x10 to 0x1F, the DSD1794 outputs some data, even if in Table 3 in Table 3 There is no definition of it. Figure 31 is a schematic diagram of reading operation.

Noise suppression

DSD1794 uses a system clock (SCK) for noise suppression. However, in 600ns, noise must not exceed two. In the fast mode, the SCK frequency of noise suppression is between 8MHz and 40MHz. However, it works abnormally under the following circumstances.

Case 1:

1, T (SCK) GT; 120 nan seconds (t (SCK): SCK cycle;

2. T (high)+t (high)+t (high)+t (high)+t (high)+t D hd) lt; t (SCK) × 5;

3. There are peak noise in the first half of the high pulse of SCL.

Speed u200bu200bnoise.

When these situations appear at the same time, the data is considered low.

Case 2:

1, T, T (SCK) gt; 120 nano seconds;

2, T (s hd) or t (RS hd) lt; t (SCK) × 5;

3 During the maintenance time, both SCL and SDA have peak noise.

When these situations appear at the same time, DSD1794 cannot detect the startup conditions.

Cases of cases 3:

1, t (SCK) lt; 50 nano seconds;

2. T (sp) gt; t (SCK);

3. SCL in SCL in SCL After falling, peak noise appears.

4. There is a peak noise on the SDA before SCL decreases.

When these situations appear at the same time, DSD1794 is wrongly detected by error detection To start or stop conditions.

Typical wiring chart

Application circuit

To truly realize the high signal -to -noise ratio that DSD1794 can achieve The design of the application circuit is very important. This is because the noise and distortion generated in the application circuit cannot be ignored.

In the circuit in FIG. 33, the output level is 2V RMS, reaching 127DB signal noise noise noise noise noise noise noise noise noise noise noise noise noise noise noise noise noise noise noise noise noise Compared. FIG. 34's circuit can achieve the highest performance. In this case, the output level is set to 4.5 V RMS to reach 129 db S/N (stereo mode). In a monocular track mode, if the L channel and R and R mode The output of the channel is used as a balanced output, and the signal -to -noise ratio of 132DB (see Figure 36).

FIG. 35 shows the circuit of the DSD mode. This is a 4 -order low -pass filter to reduce the belt External noise.

Part I/V

Each output pin (IOUTL+, IOUTL-, IOUTR+, IOUTR-) current on DSD1794 is 7.8 mA P-P at 0 dB (full marking). The voltage output level of the I/V converter (VI) is given by the following formula:

(RF: feedback resistance of I/V converter)

[

[ 123] It is recommended that the I/V circuit use the NE5534 computing amplifier to obtain the specified performance. Dynamic performance, such as gain bandwidth, stable time, and conversion rate operation amplifier to affect the audio dynamic performance.

Licoar section

DSD1794 voltage output is the differential amplifier level. They add the differential signals of each channel to form a single -end I/V operational amplifier output. In addition, the differential amplifier provides a low -pass filter function.

The computing amplifier recommended by the differential circuit is linear technology LT1028 because its input noise is very low.

The application of the external digital filter interface

and external digital filtering Application of device interface For certain applications, external digital filters may need to be used to perform internal insertions, because it can provide improved block attenuation compared to the internal digital filter of DSD1794.

DSD1794 supports a variety of external digital filters, including:

*Texas instrument DF1704 and DF1706

*Pacific Microsoft PMD200 HDCD filter IC

123]*programmable digital signal processor

Visit the external digital filter application mode by programming the following bit in the corresponding control register:

dfth 1 (register 20)

The pins of the serial interface for external digital filters are shown in the connection diagram of Figure 37. The word clock (WDCK) signal must work under the sampling frequency FS at 8 × or 4 × expected.

System clock (SCK) and interface timing

In the application of external digital filters, DSD1794 requires WDCK and system clock synchronization. The system clock is not phase relative to WDCK. The interface timing between WDCK, BCK and data is shown in Figure 39.

Audio format

DSD1794 under the interface mode of external digital filter supports right alignment audio formats, including 16 -bit, 20 -bit, and 24 -bit audio data, as shown in Figure 38. The audio format is selected by the fmt [2: 0] bit of the control register 18.

DSD format (DSD mode) interface application 123]

This mode is used directly to the DSD decoder interface, which can be found in the Super Audio CD (SACD) application.

Access the DSD mode by programming in the corresponding control register.

dsd 1 (register 20)

DSD mode provides a low -pass filtering function, converting 1 excess data flow into analog domain. Use analog FIR filter structure to provide filtering. The four FIR responses are available and are selected by the DMF [1: 0] bit of the control register 18.

DSD bits must be set before entering DSD data, otherwise DSD1794 will be mistakenly detected by TDMCA mode and cannot accept commands through serial control interface.

The pin allocation of the dsd format interface

*DSDL (pin 1): L channel DSD data input;

*DSDR (pin 2): R channel: R channel DSD data input;

*DBCK (pin 3): bit clock (BCK) of DSD data.

Simulation FIR filter performance in DSD mode

]

(1) When the DSD input signal efficiency is 50%, this gain is compared with PCM 0 DB. System clock requirements

DSD1794 pins 3 requires the bit clock (DBCK) of the DSD mode. The frequency of the bit clock can be N times of the sampling frequency. Generally, N is 64 in DSD applications. The interface between the Clock and DSDL and DSDR needs to meet the same settings and maintain time specifications, as shown in Figure 42.

Operation theory

DSD1794 adopts TI's high -level DAC architecture to achieve excellent dynamic performance and tolerance for clock shake. DSD1794 provides a balanced current output.

The digital input data of the digital filter is divided into 6 highs and 18 lows. Six highs are converted to reverse complementary offset binary (ICOB) code. The low 18-bit associated with MSB is treated by a 5-level third-order Delta-Sigma modulator, which works under 64FS. The 1 LSB of the 1 LSB of the ICOB code converter is equivalent to the 1 LSB of the ICOB code converter. In ICOThe data set processed in the B and third-order Delta-Sigma modulator is merged into a digital code of up to 66 levels, and then processed through data weighted average (DWA) to reduce the noise generated by component loss.Data from 66 levels from DWA is converted into analog output in the differential current segment.

This architecture overcomes the various shortcomings of many traditional processes, and has obtained good dynamic performance.

Simulation output

The relationship between digital input code and analog output shows the following table and Figure 52.