Features

Compared with DRV591 , the operation reduces the size and cost of the output filter 50%

]

± 3-a maximum output current

Low-voltage operation: 2.8 V to 5.5 v

# 8226;

High -efficiency generates less calories

over current and thermal protection

over Failure indicators under current, overheating and under pressure conditions

Two optional switching frequency

Internal or external clock synchronization

PWM solution optimized for EMI

9 × 9 mm power board #63722; four flat packaging packaging

Application

Thermoelectric cooler (TEC) drive

#8226

Laser diode partial pressure Instructions

DRV593

and DRV594 are high -efficiency, large current power amplifier, which is very suitable for driving 2.8 V to to 5.5 Various temperature difference cooler components in the V system. The operation of this device only requires an inductor and capacitor for output filters to save a large number of printing circuit board area. Pulse-width modulation (PWM) operation and low output-level guide resistance can significantly reduce the power consumption of the amplifier. DRV593 and DRV594 have heat overload and current overload protection inside. The logical level fault indicator signal sends a signal when the knot temperature reaches about 115 ° C, so that the system -level shutdown can be performed before the internal thermal shutdown circuit of the amplifier. When an current event occurs, the fault indicator also sends a signal. If the current circuit slice, the device is automatically reset (see the application information part for more details).

According to the system requirements, the PWM switch frequency can be set to 500 kHz or 100 kHz. In order to eliminate external quantity, the gain of DRV593 is fixed at 2.3V/V. For DRV594, the gain is fixed at 14.5V/V.

Order information

(1), this package can be rolled up with tape. wantTo order this packaging option, add an R suffix to the part number (for example, DRV593VFPR or DRV594VFPR).

Figure Figure

Typical features Figure table

graphic Test settings

The LC output filters used in Figure 2, 3, 8, and 9 are shown below.

Typical features

Application information The pulse width modulation scheme of DRV593 and DRV594 The pulse width modulation scheme implemented in DRV593 and DRV594 eliminates half of the full output filter before the PWM drive. Essence DRV593 and DRV594 only need an induction and capacitor as the output filter. H/c output determines the direction of the current, not switch back and forth. The PWM output switch generates a proportional voltage to the input control voltage on the load.

Cooling method

FIG. 18 shows the DRV593 and DRV594 in the cooling mode. H/C output (pin 14-17) ground, PWM output (pin 24-27) generates a voltage proportional to the input voltage on the load.

Determine the differential voltage on the load through the equation (1), and use the equal (2) to determine the duty cycle. The differential voltage is defined as the voltage measured by the PWM output filter relative to the H/C output.

Among them

D: PWM signal's duty cycle

AV: DRV593/594 gain (DRV593: 2.3V/V,,,,,, DRV594: 14.5V/V) VIN+: DRV593/594's positive input terminal

VIN-: DRV593/594 negative input terminal

VDD: power voltage

]

For example, as shown in Figure 18, the 50%duty cycle generates a voltage of 2.5 V within the load range of VDD 5 V.

Heating method

Figure 19 shows DRV593 and DRV594 in the heating mode. The H/C output is proportional to the voltage on the VDD, PWM output to the voltage on the load.

Determine the differential voltage on the load through the equation (3). The variables are the same as the variables used in the front for equation (1) and (2).

For example, as shown in Figure 19, the 50%duty cycle caused the voltage on the load when VDD 5 V was -2.5 V. The voltage difference on the load is defined as the voltage measured by the PWM output filter relative to the H/C output.

The heat/cold transformation

When the device transitions from cooling to heating, the duty cycle of PWM output is reduced to a small value, H/C The output is kept on the ground. When the device is converted to the heating mode, the H/C output changes from zero to VDD, and the PWM output becomes a high -duty cycle. The direction of the current is the opposite, but keeps low voltage on the load. When the component enters the heating mode further to drive more current through the load, the duty cycle is reduced. Figure 20 illustrates the transition from cooling to heating.

Over zero area

When the output voltage of the differential output is close to zero, the control logic in DRV593 and DRV594 makes the output change between heating and cooling mode. Both outputs can be a zero voltage output, or the two voltage difference output. Therefore, when the two input voltage is equal, random noise will cause the output to change between the two states. The output is switched from zero to VDD, although it is not a fixed frequency. Some pulses may be wider than other pulses, but the two outputs (PWM and H/C) are tracked each other to provide zero differential voltage. These uneven pulse width will increase the switching noise under the components.

In order to avoid this phenomenon, lag should be implemented in the control circuit to prevent the device from running in the area. Although the operation plan during zero period is important, the normal operation points of DRV593 and DRV594 are outside the area. For laser temperature/wavelength adjustment, only when the laser temperature or wavelength does not require the heating or cooling of the TEC component from the environmental temperature, zero output conditions are a problem.

Precautions for the output filter

TEC component manufacturer provides the maximum DC current and maximum DC current and the maximum Electrical specifications of output voltage. However, the maximum ripple current is usually less than 10%, and the frequency component of the current is not referred to. The maximum temperature difference on the component decreases with the increase of the current wave current. The following formula calculations can be used:

where:

#8710; t Actual actuality Temperature difference

#8710; tmax maximum temperature difference (stipulated by the manufacturer)

ratio of ripple current to DC current According to this relationship, 10%of 10% The ripple current can reduce the maximum temperature difference by 1%. The LC network can be used to filter the current to TEC to reduce the amount of ripples. More importantly, the rest of the protection system is exempted from any electromagnetic interference (EMI).

Selection of filter componentsSelect

LC filter can be designed from two different angles. Both angles will be described below, which helps estimate the overall performance of the system. The design of the filter should be applied to the worst situation during operation, that is, when the differential output is at a 50%duty cycle. As the starting point of the design, any calculation should be confirmed through the prototype circuit in the laboratory.

Any filter should be as close to DRV593 and DRV594 as much as possible to reduce EMI.

The frequency domain LC filter

The transmission function of the second -order low -pass filter (Figures 17 and 18) is shown in the same formula (5):

q Quality coefficient

W DRV593 or DRV594 switch frequency

For DRV593 and DRV594, the frequency of differential output switch is usually selected as as 500 kHz. The resonance frequency of the filter is usually selected to at least one magnitude lower than the switch frequency. Then, the equation (5) can be simplified to give the following earthquake equation (6). These equations assume that the filter in Figure 22 is assumed.

fs 500kHz (DRV593 or DRV594 switch frequency)

If L 10 μH and C 10 μF, the deadline is 15.9 kHz, corresponding to 500 kHz On-off level. The ripples of the VDTEC component are about 5 mv.

The resistance of the average TEC component is 1.5 #8486; therefore the ripple current of the TEC is about 3.4 mA. Under the maximum output current of DRV593 and DRV594, the 5.4 MA corresponds to 0.11%ripple current, resulting in a minimum temperature difference of TEC components by less than 0.0001%(see equations 4).

LC filter

The ripple current of the inductor can use Formula (7) Calculation:

D Donald Compared to (0.5 worst case)

ts 1/fs 1/500 kitten

When VO 5V, VTEC 2.5V, L 10 μH, the electromotive ripple current is the current is the current is 250mA. However, to calculate how many ripple current flows through the TEC component, the characteristics of the filter capacitor must be considered.

A relatively small capacitor (less than 22 μF) with a relatively low equivalent series resistance (ESR, less than 10 m #8486; less than 10 m #8486;), such as ceramic capacitors, can use the following equal formula (8) to estimate above Capacitors caused by changes in ripple voltage charge:

d Doly -occupying ratio

For L 10 μH and C 10 μF, the deadline FO is 15.9 kHz. For the worst case of 0.5 V and VTEC 2.5 V, the ripple voltage on the capacitor is 6.2 MV. The ripple current can be calculated by removing the ripple voltage with a TEC resistor of 1.5 #8486; to obtain a ripple current through the TEC component to 4.1mA. Please note that this is similar to the value category calculated using the frequency domain method.

Large capacitors (greater than 22 μF) with higher ESR (greater than 100 m #8486; greater than 22 μF), such as electrolytic capacitors, ESR lead capacitors. Can be used as a simple program (9) to estimate the ripple voltage:

#8710;/L inductive ripple current

#8710; ESR filter capacitor ESR

For 100 μF electrolytic capacitors, ESR is usually 0.1 #8486; If you use a 10 μH electrical sensor and provide a capacitor with a capacitor of 250 mAh (calculated above), the ripple voltage is 25 millivol. This is more than 10 times that of 10 μF ceramic capacitors, because ESR of ceramic capacitors can usually ignore.

Switching frequency configuration: oscillator component ROSC and COSC

and frequency operation

The laying slope generator requires an external resistor and capacitor to set the oscillation frequency. By selecting the appropriate capacitor value and maintaining the frequency pins to low (500 kHz) or high (100 kHz), the frequency can be 500 kHz or 100 kHz. Table 1 shows the value and frequency pin configuration required for each switch frequency.

In order to correctly operate, the resistance ROSC should have 1%tolerance, and the capacitor COSC should be ceramic type with a tolerance of 10%. Both components should be grounded to the agng. Agnd should be connected to PGND at one point, usually places where the power and ground physical connection to the printing circuit board.

External clock operation

To switch to the external clock signal simultaneously, lower the int/ext end, and drive the clock signal to the COSC terminal. The clock signal must be within the range of 10%to 90%, and meets the voltage requirements specified in the electrical specification table. Because DRV593 and DRV594 include an internal multiplier, the external clock signal must be about 250 kHz. Allows to deviate from 250 KHz clock frequency and stipulate in the electrical characteristic table. In this operation mode, the resistor connected from ROSC to ground can be omitted from the circuit. The power supply is disconnected inside.

Enter configuration: Differential single -end

If the input of the fruit is used, it should be biased near the mid -rail of the DRV593 or DRV594, and it shall not exceed the input range of the input level (see the operating characteristics of the data at the beginning of the data).

The most common configuration is to use single -end input. Unused inputs should be connected to VDD/2, which can be simply implemented with a resistor. In order to obtain the best performance, the selected resistance value should be 100 times lower than the input resistance of DRV593 or DRV594. This prevents the offset of the bias voltage of the unused input terminal when the signal is applied. A small ceramic capacitor should be placed from the input end to the ground to filter the noise and keep the voltage stable. The computing amplifier configured to the buffer can also be used to set the voltage of the input -end.

Fixed internal gain

Differential output voltage can be used in equations (10) Calculation:

AV is voltage gain, DRV593 internal fixation is fixed to 2.3 V/V, DRV594 is fixed to 14.5 V/V internally. The electrical specifications at the beginning of the data surface provide the maximum and minimum rated value.

Power supply decoupling

In order to reduce the impact of high -frequency transient or peaks, a small ceramic capacitor (usually 0.1 μF to 1 μF) should be as close to the DRV593 and DRV594 PVDDs as much as possible. foot. For overall decoupling, 10 μF to 100 μF 钽 钽 or aluminum electrolytic capacitors should be placed in a relatively close to DRV593 and DRV594.

Aref capacitor

Aref terminal is the output of the internal mid -rail voltage regulator of the car oscillator and the slope generator. The regulator shall not be used to supply any additional circuit. In order to maintain stability, 1 μF ceramic capacitors must be connected from Aref to Agnd (about the Agnd connection information, please refer to the above oscillator components).

Torter operation

DRV593 and DRV594 include a closing mode that can disable the output and place the device in the low power current state. The stop pin can be controlled by the TTL logic signal. When the shutdown is kept at high, the device is running normally. When the shutdown is kept at low, the device is in a state of stopping. Disclosure is not allowed to keep floating. If the shutdown function is not used, the pin can be connected to the VDD.

Failure report

DRV593 and DRV594 include three types of faults:

*over current

*IOU

* Over -temperature

These three types of failure are decoded through the Fault1 and Fault0 terminals. Internally, these are the leakage output, so a 5 k #8486; or a larger external pull -up resistor.

When the output current exceeds 4 ampels, it reports the current failure. Once this situation is detected, over -current failure is set, and the output enters a high impedance state about 3 μs to 5 μs (500 kHz operations). After 3 μs to 5 μs, the output is re -enabled. If the current state is over, the fault is cleared, and the device is restored to normal operation. If the current still exists, repeat the above order.

When the operating voltage drops below 2.8V, the report of the report is wrong. The failure is not locked, so once the power supply is restored, the fault is cleared, and the normal operation is restored. Under the underwriting conditions, the output will enter a high impedance state to prevent excessive launch caused by increasing RDS (on).

When the knot temperature exceeds 115 ° C, it reports an ultra -temperature failure. The device continues to work normally until the knot temperature reaches 150 ° C. At this time, the IC is disabled to prevent permanent damage. Once the ultra -temperature flag is set, the system controller must reduce the power required for DRV593 or DRV594, otherwise the device will be closed when the temperature reaches 150 ° C. This failure will not be locked; once the knot temperature drops below 115 ° C, the fault will be cleared and the normal operation will be restored.

Power consumption and maximum environmental temperature

Although DRV593 and DRV594 are much more efficient than traditional linear solutions, the power drop on the output transistor pirate resistance will indeed generate some calories in the packaging pack The calculation method is as shown in the equal formula (11):

For example, the total pirate resistance is 130 m #8486; (at TJ 25 ° C)) The maximum output current is 3 A, and the power consumed in the package is 1.17 W.

Use Formula (12) Calculate the highest ambient temperature:

Print circuit board (PCB) layout precautions

due to DRV593 and DRV594 It is a large current switching device. Some guidance principles of the printing circuit board (PCB) layout must be considered:

1. ground. The simulation ground (AGND) and the power ground (PGND) must be separated. In ideal, return to the position of the power physical connection to the PCB, and return to the bulk off -coupled capacitor (minimum value of 10 μF ceramics). In addition, the grounding connection of the power board should be connected to AGND instead of PGND. Agnd or PGND is not recommended to use ground layers, and the trace line should be used to determine the current path. Wide lanes (100 dense ears) are applied to PGND, narrow (15 dense ear) are applied to AGND.

2. Power supply decoupling. The μF ceramic capacitor of small 0.1 μ to the first floor should be as close to each set of PVDD pins as much as possible, and connect to PGND from PVDD to PGND. 0.1 μF to 1 μF ceramic capacitor should also be placed near the AVDD pin, from AVDD is connected to agng. At least 10 overall off -coupled capacitors μF, preferably ceramics, should be placed near DRV593 or DRV594, from PVDD to PGND. If the power cord is longer, extra decoupling may be needed.

3. Power and output trajectory. The power and output trajectory should be able to handle the maximum output current. The output trajectory should be as short as possible to reduce the electromagnetic interference, that is, the output filter should be as close to the DRV593 or DRV594 output as much as possible.

4. Power board. Drv593 and DRV594 in the four flat packaging packaging use TI PowerPad technology to enhance thermal performance. PowerPad physical connection to DRV593 and DRV594 silicon lining, DRV594 silicon is connected to agng. Therefore, as mentioned above, the grounding connection of the power board should be separated from PGND. Agnd can be connected below the power board to facilitate ground. For more information about the layout of PowerPad PCB, see PowerPad thermal enhanced package application description SLMA002.

5. Thermal performance. In order to obtain appropriate thermal performance, PowerPad must be welded into the thermal pad, as described in SLMA002 as the PowerPad thermal enhanced packaging application description. In addition, at a high current (greater than 2A) or high environmental temperature (greater than 25 ° C), the internal plane can be used for heat dissipation. The passage under the power board should be firmly connected. Unless the power board is connected, the aircraft shall not be connected to the ground, as described above.