Features

Dual -pole output: up to ± 16V

Single output: 0V to+20V

16 Summary

relative accuracy: maximum 1 lsb

low zero point and gain error

- Before user calibration: 4 lsb

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123] - Vibration after user CA: 0.125 LSB zero error, 1 LSB gain error

Low noise: 60nv/√Hz

Settlement time [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 [123 ]

Available gain: x2/x4

Simulation output monitor

8226; SPI #8482;: up to 50MHz, 1.8V/3V/5V logic

chrysanthemum chain mode

operating temperature: -40 ° C to +105 ° C

Packaging: QFN-40 (6x6mm), TQFP-48 (7x7mm)

Automatic testing equipment

Instrument

Industrial process control

Communication

Instructions

dac8734 [ 123] It is a high -precision, four -channel, 16 -bit digital module converter (DAC). In the bipolar output mode, it can work within the power supply voltage range of ± 5V to ± 18V. 5V to+24V/-12V working mode. As a 5V benchmark, DAC8734 can be configured to output ± 10V, ± 5V, 0V to 20V or 0V to 10V. DAC8734 provides 16-bit monotonicity, within the working temperature range of -40 ° C to+105 ° C. The excellent integral non-linear (INL) error is ± 1 LSB, low failure and low noise. The device was fine -tuned in production to obtain very low zero points and gain errors. In addition, the DAC8734 realizes user programming system -level calibration function to achieve ± 0.125 LSB zero error and ± 1 LSB gain error.

DAC8734 has an integrated reference buffer and output buffer. It has a standard high -speed 1.8V, 3V or 5V serial peripheral interface (SPI), and its working clock frequency is as high as 50MHz, which can communicate with DSP or microprocessors. Four DAC channels and supplementsThe register is addressing with four addresses. The device has a dual buffer interface logic, which can be updated at the same time. The asynchronous load input (LDAC) transmits the data from the input data register to the DAC memory, and the content setting voltage of the content settings of the DAC memory. The asynchronous RST input sets the output of all four DACs to 0V. The VMON pin is an analog monitor output, using a single DAC output or AIN pin.

DAC8734 and DAC8234 (14 -bit) and DAC7716 (12 -bit) pins.

Figure Figure

Typical features

[ 123]

Operation theory DAC architecture [ 123] DAC8734 is a highly integrated four -channel 16 -bit voltage output DAC with internal reference buffer and output buffer. Each channel consists of an R-2R trapezoidal structure, three of which are segmented by MSB, and then an operational amplifier, as shown in Figure 41. DAC8734 has high impedance, buffer reference input; reference buffer output drive R-2R trapezoid diagram. The design of the output buffer allows users to adjust the configurable adjustment, providing four different output voltage range settings for DAC8734. After production debugging, the device has excellent DC accuracy and communication performance.

Channel Group

Four DAC channels are divided into two groups (A and B), each group has two channels. Group A consists of DAC-0 and DAC-1, and Group B consists of DAC-2 and DAC-3. The two DAC channels in group A obtained reference voltage from Ref-A, and the DAC channel of Group B obtained reference voltage from the REF-B.

User calibration of zero errors and gain errors

DAC8734 realizes user calibration function, allowing fine -tuning system gain and zero errors. Each DAC channel has a gain register and zero register, and calibrate the DAC output based on the value of the corresponding register. The range of gain adjustment is usually ± 0.195%of the full marking degree, 1 LSB per level. Zero code adjustment is usually ± 0.0488%of the full range, 0.125 LSB per level. The input data format of the gain register and the zero register is two supplements. See Table 9 and Table 10 for details.

If system -level calibration is not required, these registers should maintain their default values (0000h) during power.

The transmission function of the analog output (VOUT-0 to VOUT-3)

For dualExtreme output:

where:

The gain is DAC gain, which can be set to X2 or X4, from the pin RFB1-X and RFB2-X to VOUT -X, and the gain position in the command register.

Input U Code is a decimal equivalent value of the code that writes the code in the DAC input register.

Zero_Code is the decimal value of the code of the code of the zero register.

Gain_code is the decimal value of the code of the code of the gain register.

Note that the output voltage must not be greater than (AVDD – 1.0V) or less than (AVSS+1.0V); otherwise, the output may be saturated.

Input data format

For the bipolar output operation, the input _ code always has two supplements, which can accept the value between -32768 to 32767.

For the single output operation, the input code is always direct binary and can accept the value between 0 and 65535.

GAIN_ code always adopts the TWOS supplementary code format, which can accept the value between -128 to +127.

Zero_ code is always the TWO-S complement format, which can accept the value between -256 and +255.

The data of the writing command register and the monitor register is written in accordance with the provisions in the definition. For reading operations, the return data format is the same as the format for writing the device. For details, see the internal register part.

Output range

Each channel of DAC8734 implements an output amplifier, which provides single -pole output or bipolar output with a gain of 2 or 4. The output range is equivalent to gain multiplied by reference voltage. For 5V reference, the output range can be configured to ± 10V, ± 5V, 0V to 20V or 0V to 10V. The state of the Uni/BIP pin determines the output mode (single or bipolar) of each group. When the UNI/BIP-A pin is high, the output of the group A (DAC-0 and DAC-1) is the single pole; when the pin is low, the output of the group A is bipolar. Similarly, the UNI/BIP-B pins define the output mode of group B (DAC-2 and DAC-3).

Each individual DAC can be configured to gain 4 or gain 2. To set up gain 4, connect RFB1-X to Vout-X when RFB2-X keep opening, and set the gain bit of the channel to 1 in the command register. To set up gain 2, connect RFB1-X and RFB2-X to VOUT-X, and set the gain level of the channel to 0 . When powering or reset, the gain level in the command register is set to 1 by default. If the gain 2, it must be cleared to 0 Essence

Please note that the power supply must meet the following requirements:

AVDD must not be greater than 24V or less than 4.75V, and AVSS must not be greater than –4.75V or less than –18V. In any case, (AVDD -AVSS) ≤36V.

For bipolar mode: AVDD ≥ 2 × VREF+1V, and AVSS ≤ – 2 × VREF -1V.

For polar patterns, ≤1vref -1vref, ≤1vref.

For example, for the 5V reference voltage in the bipolar operation, whether the output range is ± 5V or ± 10V, the minimum power supply must be at least ± 11V. For monocular operations with the same benchmark, the power supply must be at least ± 11V (for 0V to 10V operations), and+21V/– 11V (for 0V to+20V operations).

Update DAC output

DAC8734 has a dual buffer interface, each channel consists of two registers: input register and DAC memory. The digital code is transmitted from the SPI displacement register to the addressing channel input register after the effective writing sequence is completed. DAC 包 locks contain the digital code used by the resistor R-2R trapezoid diagram. The content of the DAC memory defines the output of DAC. DAC output can be updated separately or at the same time. DAC8734 only updates the DAC 闩 lock only after the LD bit of the LDAC pin decreases or the command register is set to 1 , thereby eliminating any unnecessary failure. The DAC channels that have not been accessed will not be reloaded and the output value remains unchanged.

A single DAC channel update

In this mode, the LDAC pin is kept at a low level, and the CS pin is at a low level. The data is sent to the SPI displacement register by the clock. At the end of the data transmission to the displacement register, the CS pin was raised. This operation also updates the addressing data register and the corresponding DAC lock register. DAC lock register controls the R-2R switch; therefore, the corresponding DAC channel simulation output of the DAC lock register.

Update multiple DAC channels at the same time

In this mode, LDAC pin keeps high level, while CS pin is at low level, data is sent to the SPI displacement register by the clock to the clock. Essence At the end of the data transmission to the displacement register, the CS pin was raised. This operation only updates the addressing input data register; it does not update the DAC lock register or changes the output. When the analog data is written in the register, the LDC data is written in low in the register.

Hardware reset

When the RST pin is low, the device is in the state of hardware reset. All analog outputs (VOUT-0 to VOUT-3), input storageBoth the device and the DAC memory device are set to the reassignment value shown in Table 1. All registers are loaded by the default value. The communication was disabled, and the signals on the SDI, CS, and SCLK pins were ignored. At the rising edge of the RST pin, the simulation output (VOUT-0 to VOUT-3) keeps the reset value (0V) until the new value of programming. After the RST pin becomes higher, the device will return to normal operation. Note that after reset, the default value of the increase in the command register is 1 . For gain 2, the gain position must be cleared to 0 .

The first place in the command register is set to 1 to execute software resetting, which is the same functional as hardware reset. After the reset is completed, the first place automatically returns 0 .

Powering and reset

When powering, the input data register and DAC lock memory load the value defined by the UNI/BIP pin (see Table 1). All other registers are loaded by the default value. After power -on, the output setting of the VOUT pin is 0V.

Simulation output monitor pins (VMON)

VMON pin is an analog output monitor. The function of analog output monitor includes an analog multi -road multiplex with a serial interface addressing, allowing one or Ain input route in the four channel output to monitor this tube foot. The monitor function is controlled by the monitor register and allows enable or disable monitoring output. When all multi -way reuse channels are disabled, the monitor output is high impedance; therefore, several monitor outputs can be connected in parallel and can only be connected at a time. Table 5 shows settings related to the monitor function.

Note that the multi -way relics are realized as a series of simulation switches. It should be noted that the maximum current from the VMON pin must not be greater than the given specifications, because this situation may cause a large amount of current to flow from the input of the multi-way reusrator (that is, from VOUT-X or Ain) to the multi-way reusrator ( VMON) output. In addition, the VMON pins output impedance is about 2.2k #8486; therefore, the high -impedance input measurement VMON should be used.

Power off mode

DAC8734 realizes the power -breaking function to reduce power consumption in some channels. When the power-off level (PD-A and/or PD-B) in the command register is set to 1 , the corresponding group enters the power-off state. During the power -off, the reference buffer and output buffer of the group were powered off, and the corresponding analog output was set to 0V to Agnd through an internal 10K #8486; the resistor was set to 0V to agng. The content of the internal register is unchanged, and the bus interface is maintained in order to continue communication and receive commands from the host controller. Any internal register can be read and write. The host controller can wake up the device from the power-off mode and return to the normal working mode by clearing the power-off level (PD-A and/or PD-B) in the command register. The restoration is completed in about 50 microseconds.

Power supplySort

In order to ensure the correct initialization of DAC8734, it is necessary to apply digital power (DVDD and IOVDD) and logic input (UNI/BIP-X) before AVSS and AVDD. In addition, AVSS must be applied before AVDD, unless the two can be improved at the same time. Ref-X should be applied after AVDD appears to ensure that the ESD protection circuit will not be turned on.

General input/output pins (GPIO-0, -1)

GPIO-0 and GPIO-1 pins are universal, two-way, digital input/output (I/O (I/O (I/O (I/O (I/O ) Signal, as shown in Figure 42. These pins can receive input or generate output. When the GPIO-N pins are used as the output, it has an open leak, and the state is determined by the corresponding GPIO-N bit of the command register. When the GPIO-N bit is set to 1 , the output state is high impedance; when the GPIO-N bit is cleared ( 0 ), the output state is low. Note that when using GPIO-N pins as output, a pull-up resistor of 10K #8486;

To use GPIO-N pins as input, the GPIO-N bit in the command register must be set to 1 . When the GPIO-N tube foot is used as an input, the GPIO-N bit is read to obtain the digital value on the tube foot.

After the power-on reset or any forced hardware or software reset, all GPIO-N bits are set to 1 , and the GPIO-N pins enter a high impedance state.

Serial interface

DAC8734 control through a universal three -line serial interface. Compatible #8482;, Microfi #8482;, and DSP #8482; standards.

SPI displacement register

The width of the SPI displacement register is 24 bits. Under the control of SCLK in the serial clock, the data is first loaded as a 24 -bit word into the device MSB. The decline of the CS starts to communicate. When the CS is low, the data is locked to the SPI displacement register where the SCLK is reduced. When CS is high, SCLK is blocked, SDI is ignored, and the SDO line is in a high impedance state. The content of the SPI displacement register is loaded to the internal register of the address of the CS rising edge. The SPI displacement register consists of a read/writing position, the address bit of the four registers, the 16 data bit, and the three reservations, as shown in Table 2. The time of this operation is arranged in the sequential map section. When the device is loaded, the command is decoded and the new data is transmitted to the appropriate data register.

The serial interface can be used for continuous and non -continuous serial clocks. The continuous SCLK source can only be used when the CS is kept at a low clock cycle. During the door controlIn the clock mode mode, a sudden clock containing a precise clock cycle must be used, and higher CS must be taken after the last clock to save data.

Single -machine operation

The first decline of CS began to run cycle. Before CS returns to the high position again, it must be applied to 24 clocks to drop edges. If CS rises before the 24th SCLK declines, the data is ignored. If more than 24 SCLKs are applied before CS gets higher, the last 24 bits are considered. The internal register of the address is updated from the shift register of the CS rising edge. In order to perform another serial transmission, CS must be lowered again.

When the selected registers of the DAC transmitted to the addressing DAC, all DAC locks and analog outputs can be updated through LDAC pins or set LD bits in the command register.

The operation of the chrysanthemum chain

For a system containing multiple devices, the SDO pin can be used for multiple devices of the chrysanthemum chain. The chrysanthemum chain operation can be used to diagnose and reduce the number of serial interface lines. Note that before the operation of the chrysanthemum chain, the SDO pin must be enabled by clearing the command register (dsdo #39; 0 #39;). By default, the position was cleared after power -on or reset. The first decline of CS started running cycle. When CS is low, SCLK is continuously applied to input displacement registers. If there are more than 24 clock pulses applied, the data will fluctuate from the displacement register and appear on the SDO line. The data on these ups and downs are effective. By connecting the SDO output of the first device to the SDI input of the next device in the chain, a multi -device interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must be equal to 24 × n, where N is the total number of DAC8734 in the chain. When the serial transmission of all devices is completed, CS takes a high value. This operation locks the data from the SPI displacement register to the device input register of each device in each device in the chrysanthemum chain, and prevent any further data from being entered by the clock.

Reading operation

The read command is used to start the recovery operation. However, before starting the recovery operation, the SDO PIN must be enabled by removing the DSDO bit (DSDO #39; 0 #39;) in the command register; Then perform a Read command (r/w bit #39; 1 #39; see Table 2) to start the recovery operation. Read the bit A3 to A0 in the read command to select the register to be read. The remaining data in the command is indifferent. During the next SPI operation, the data appearing on the SDO output comes from the previous addressing register. For reading for a single register, you can use the NOP command to output data from the selected register from the selected register on the SDO. IfIf you read multiple read commands, you can read multiple registers. The readback diagram in FIG. 43 shows the reading sequence. Reading the data format is the same as the format for writing the device.

Application information

Basic operation

DAC8734 is a highly integrated device, with high -performance reference buffer and output buffer The device greatly reduces the area and cost of the printing circuit board (PCB). The reference buffer on the film eliminates the need for negative external benchmarks. The output buffer on the configuration film supports four different output modes. Figure 44 shows the basic application of DAC8734.

User zero point and gain calibration

During the production process, DAC8734 was fine -tuned under the nominal working conditions, so that it had very low gain errors. And offset error. However, in order to trim the offset and gain error introduced by other components in other operating conditions or by other components in the signal chain, the DAC8734 has zero -point and gain digital calibration characteristics for each DAC channel. Figures 45 and Figure 46 respectively illustrate the zero point and gain calibration of DAC8734 in single -pole output and bipolar output configuration.

System zero -for example

In the 20V output range, the DAC8734 zero -point calibration function can reduce the system's offset error to 0.00019%FSR or 38 μV. The total adjustment range is about ± 0.0488%of FSR, or ± 9.7mV of the 20V output range.

Assuming that the full marking range of the DAC is 20V, the offset error eliminated from the signal chain is -1MV, the step length 0.0000019 × 20V 38 μV.

Among them, offset_error is a correct offset error value.

In this example, the number of zero steps 1mv/38 μV≈26. Therefore, zero registers should be encoded with two supplements of 26 0 0001 1010.

Assuming the offset error to be eliminated is+1MV, the number of steps calibrated at zero-point calibration is two supplementary codes of -26, that is, 111010110.

System gain adjustment example

In the 20V output range, the DAC8734 gain calibration function can reduce the system gain error to 0.001525%FSR or 305μV. The total adjustment range is about ± 0.195%FSR, or the range of 20V output is -39mv to+38.7mv.

Assuming that the full marking range of the DAC is 20V, the gain error that eliminate from the signal chain is -10mv, then the step length 0.00001525 × 20V 305μV.123]

Among them, gain_error is the gain error value to be corrected.

In this example, the number of step calibrations 10mv/305μv≈33. Therefore, the gain register should be encoded with two supplements of 33 0010 0001.

Assuming the gain error to be eliminated is+10mV, the number of step calibration steps is the two supplementary equivalent of -33, that is, 1101111.

Arranging and grounding

The precise simulation circuit requires a careful layout, sufficient bypass electrical container, and clean and well -adjusted power supply to obtain the best DC and AC performance. Careful considering the power supply and grounding circuit layout can help ensure rated performance.

The design of the PCB must separate the simulation and the digital part and limit it to some areas of the circuit board. Quick switching signals, such as clocks, must be shielded with digital grounding to avoid radiation noise to other parts of the circuit board, and must not run nearby input. The important thing is to minimize the reference input noise, because it is coupled to DAC output. Avoid digital and analog signal crossing. The trails on both sides of the circuit board must be right angles. This configuration reduces the feeding effect on the line board. You can consider micro -band technology, but it is not always feasible on the double panel. In this technology, the component side of the circuit board is dedicated to the ground plane, and the signal wire is placed on the welded side.

DGND is the return path of digital current, and AGND is the simulation power source of DAC. In order to obtain the best AC performance, pay attention to connecting DGND and agng with extremely low resistance back to the power supply. If multiple devices need to be connected to DGNNN, it can only be connected at one point. Star -shaped locations must be as close to the device as possible. Each DAC has a grounding pin (SGND-X), which must be directly connected to the corresponding reference grounding in the low impedance path to get the best performance. SGND-0 and SGND-1 must be connected to Refgnd-A, SGND-2 and SGND-3 must be connected to Refgnd-B. In order to prevent the linearity and gain of the voltage on the path, the tracking resistance must be very small. Reference ground pins Refgnd-A and Refgnd-B must be connected to analog ground Agnd.

Power noise

DAC8734 should have a sufficient power byher by 1 μF to 10 μF, 0.1 μF parallel on each power supply, and the location should be as close beside. 1 μF to 10 μF capacitors must be beaded. 0.1 μF capacitors must have low -effective series resistance (ESR) and low -effective series inductors (ESI), such as ordinary ceramic types. They provide low impedance grounding path under high frequency to process the transient current generated due to internal logic switches. The power cord must be usedAs wide as possible to provide low impedance paths and reduce the impact of faults on the power cord. In addition, the broadband noise on AVDD, AVSS, DVD and IOVDD power supply should be filtered before entering DAC to obtain the best noise performance.

Selection of precision voltage benchmark

In order to make DAC8734 achieve the best performance throughout its working temperature range, precision reference voltage must be used. Consider selection of precision reference voltage. DAC8734 has two reference inputs, REF-A and Ref-B. The voltage applied to the input input is used to provide a positive reference and negative reference for the core of DAC. Therefore, any error in the voltage benchmark is reflected in the output of the device. When selecting the voltage base for high -precision applications, there are four possible sources of error: initial accuracy, temperature coefficient of output voltage, long -term drift and output voltage noise. The initial accuracy error of the external benchmark output voltage can cause the full standard error in the DAC. Therefore, in order to minimize these errors, the first choice has a benchmark with low initial accuracy error specifications. Long -term drift is the degree of measuring reference output voltage over time drift. Cferences with strict long -term drifting specifications ensure that the entire solution is relatively stable throughout its entire life cycle. The temperature coefficient of reference output voltage affect INL, DNL, gain error and zero error. Select a benchmark with strict temperature coefficient specifications to reduce the dependence of DAC output voltage on environmental conditions. In high -precision applications with relatively low noise budget, reference output voltage noise must be considered. It is important to choose an output noise voltage as low as possible to meet the required system resolution. Precision voltage benchmarks, such as TI Ref50xx (2V to 5V) and Ref32xx (1.25V to 4V), provide low drift and high -precision reference voltage.