Features

● Low power: 20MW

● Single or bipolar operations

● Settlement time: 10 μs to 0.012%

● 12 Line lineivity and monotonism: –40 ° C to+85 ° C

● Substant to medium scale ( DAC7624 ) or zero scale ( DAC7625 ) [123) [123) ]

● Data Reading

● Dual cushioning data input

Application

● Process control

● ATE pin electronic equipment

● Closed -loop servo control

● Electric control

● Data collection system

● Each needle digital modulus programmer

Instructions

]

DAC7624 and DAC7625 are 12 -bit four -way voltage output digital modular converters, which guarantees 12 -bit monotonous performance within the specified temperature range. They accept 12 -bit parallel input data, with dual -cushioning DAC input logic (allowing all DACs to be updated at the same time), and providing a reading mode of internal input register. The asynchronous reset clears the medium size code of all registers to 800h (DAC7624) or zero scale of 000H (DAC7625). DAC7624 and DAC7625 can work through a single+5V power supply or+5V and -5V power supply.

The low power consumption and small size of each DAC make DAC7624 and DAC7625 become an ideal choice for automatic testing equipment, daC programmer, data collection system and closed -loop servo control. DAC7624 and DAC7625 have 28-pin dual-wide plastic or 28-core SOIC packaging, which provides guaranteed specifications within the temperature range of -40 ° C to+85 ° C.

Typical performance curve: vss 0V

TA +25 ° C, VDD +5V, vss 0V, vREFH +2.5V, VREFH +2.5V, VREFH VREFL 0V, representing units, unless there are other regulations.

Typical performance curve: vss --5v

ta +25 ° C, VDD +5V, VSS –5V, VREFH +2.5V, VREFL –2.5V, representing units, unless there are other regulations.

Operation Theory

DAC7624 and DAC7625 are four roads, voltage output, 12 -digit mode conversion Device (DAC). ShouldThe architecture is a typical R-2R trapezoidal structure, which is a computing amplifier used as a buffer. Each DAC has its own R-2R trapezoidal network and output computing amplifier, but shared the reference voltage input. The minimum voltage output ( zero standard ) and maximum voltage output ( full marking ) are set by the external voltage benchmark (VREFL and VREFH). Digital input is a 12 -bit parallel word, and the DAC input register provides a reading function. The converter can be powered by a single+5V power supply or dual ± 5V power supply. Each device provides a reset function, and immediately sets all DAC output voltage and DAC registers to medium (DAC7624, code 800h) or zero scale (DAC7625, code 000H). The basic operations of DAC7624/25 are shown in Figure 1 and 2.

Simulation output

When VSS --5V (dual power operation), the output amplifier can swing in the 2.25V range of the power rail. , Ensure that the temperature range is between -40 ° C and+85 ° C. When VSS 0V (single power operation), the output can swing to the ground. Note that the stability time of the output operation amplifier will be longer, and the voltage is very close to the ground. In addition, when VSS 0V, you must be careful when measured the zero -scale error. Since the output voltage cannot swing below the ground, if the output amplifier has negative offset, the output voltage of the first few digital input code (000H, 001H, 002H, etc.) may not change.

In some applications, the behavior of the output amplifier may be crucial. In short circuits (DAC output short circuit), the current absorbed by the output amplifier is much larger than the current it can provide. For detailed information about short -circuit current, see the specification table.

Reference input

Reference input VREFL and VREFH can be any voltage between VSS+2.25V and VDD-2.25V, provided that VREFH is at least 1.25V larger than VREFL. The minimum output of each DAC is equal to VREFL plus a small offset voltage (essentially, output of the offset of the offset). Maximum output is equal to VREFH plus similar offset voltage. Please note that VSS (negative power) must be grounded or must be within -4.75V to -5.25V. The voltage on the VSS sets multiple bias points in the converter. If the VSS is not in any of these two configurations, the deviation may be error and cannot guarantee the normal operation of the device.

The current entering VREFH input depends on the DAC output voltage, which can ranging from a few micro -security to about 0.5 dollars. VREFH power does not need to absorb current, just provide power. It is strongly recommended to place at least one 0.1UF capacitor near DAC7624/25 to bypass the reference voltage.

Digital interface

Table 1 shows the basic control logic of DAC7624/25. Please note that each internal register is triggered by the level, not the edge triggers. When the appropriate signal is low, the register becomes transparent. When this signal returns high levels, the current number in the register is to lock the first group of registers (input registers) to trigger through A0, A1, R/W, and CS input. At any given time, only one of these registers is transparent. When the LDAC input is pulled down, the second set of registers (DAC registers) is transparent.

Each DAC can be updated by writing an appropriate input register, and then updated the DAC register to update independently. Alternatively, by keeping the LDAC low, the entire DAC register set can be configured to always be transparent. When writing into the input register, DAC updates will occur.

The design of the dual cushioning structure is mainly to allow each DAC input register to write at any time, and then update all DAC voltage by pulling down LDAC. It also allows to write a DAC input register at any point and change the DAC voltage by synchronizing the trigger signal connected to the LDAC.

Digital timing

Figure 3 and Table II provide detailed time sequential time for DAC7624 and DAC7625 digital interfaces.

Digital input encoding

DAC7624 and DAC7625 input data adopt a direct binary format. The output voltage is given by the following formula:

Among them, n is the digital input code. This equation does not include the effects of offset (zero standard) or gain (full marking) error.