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2022-09-16 16:00:09
DAC715 is a 16 -bit digital modulus converter with 16 -bit bus interface
Features
● High -speed 16 -bit parallel dual -cushioned interface
● Voltage output: 0 to+10V
● 13, 14, 15 linear level
● 16 -bit monotonous super temperature (L level)
● Power consumption: maximum 600MW
● Automatic adjustment of gain compensation and D/A converter
● 28 -引线DIP和SOIC封装说明 When working under the power supply of ± 12V or ± 15V, the output voltage range is 0 to+10V. The design of gain and bilateral offset adjustment allows them to set the converter output amplifier through the external potentiometer or the external D/A.28 -stitch DAC715 uses 0.3 -inch plastic impregnation and wide -body plastic SOIC packaging. The temperature range of DAC715P, U, PB, and UB is -40 ° C to+85 ° C, while the temperature range of DAC715PK, UK, PL, and UL is 0 ° C to+70 ° C.
TA +25 ° C, VCC ± 15V, unless there is another instructions.
Linear error
Linear error definition is defined as simulation output and transmission characteristic endpoint drawing drawing The deviation of the straight line.
Micro -dividing linear error
Differential linear error (DLE) refers to the output change from one adjacent state to the next state. When the digital input code changes from a code to a adjacent code word, its output step is 1/2LSB ~ 3/2LSB. If DLE is greater than -1LSB, D/A is considered monotonous.
monotonicity
If the output increases or remains unchanged to increase the digital input value, the D/A converter is monotonous. For performance level DAC715P/U, DAC715PB/UB, DAC715PK/UK and DAC715PL/UL, the monotonicity of DAC715 is guaranteed within the specification temperature range of 13, 14, 15, and 16.
Settlement time
Stability time refers to the total time (including conversion time) in the error zone near its final value after the input is changed. For 10V and 1LSBThe output level changes, the set stability time is within the ± 0.003%range of the full marking range (FSR). The change of 1LSB is measured at the main advancement (FFFFH to 0000h, 0000h to FFFFH: BTC code), which is the input conversion of stable time for the worst situation.
Total harmonic distortion
The general harmonic distortion is defined as the ratio of the square root to the square and the base frequency value of the harmonic value. Donate by the inferior frequency amplitude of the sampling rate FS.
Sinad (SINAD)
In addition to quantification and internal random noise power, SINAD also includes all harmonic components and prominent bruises in the definition of output noise power. Under the specified input frequency and sampling rate FS, Sinad is represented by DB.
Digital mold fault pulse
When the input is changed, the charge of the simulation output is injected into the simulation output from the digital input. It is measured at the half scale of the input code, and the excess of the switch as much as possible has changed the status from FFFFH to 0000h.
Digital feedback
When D/A is not selected, the high -frequency logic activity on the digital input is displayed as output noise by device coupling merger. This noise is digital feedback.
Operation
DAC715 is a single -chip integrated circuit 16 -bit D/A converter with 16 -bit D/A switch and trapezoid network, voltage benchmark, output amplifier and microprocessor bus bus line interface.
Interface logic
DAC715 has a dual -cushioning data lock. Enter the data locks to save a 16 -bit data word, and then load it to the second lock (D/A lock memory). This dual buffer structure allows to update multiple D/A converters at the same time. All digital control input low levels are effective. Refer to the box diagram shown in Figure 1.
All locks are triggered horizontally. The data that appears when the input is enabled as the logic 0 will enter the locks. When enable input to return logic 1 , the data is locked.
CLR input reset the input lock and D/A locks to provide semi -standard output.
Logic input compatibility
DAC715 digital input is TTL compatibility (1.4V switching level), low leakage, high impedance. Therefore, input is suitable for 5V logic families, such as CMOS logic. The equivalent circuit of the digital input is shown in Figure 2.
If it is not connected, the input will float to the logic 0 . It is recommended to connect any unused input to DCOM to improve noise resistance.
When the power supply is closed, the digital input remains high impedance.
Enter coding
DAC715 is designed to accept the dipperm code (BTC) input code for binary 2. For a singleExtreme simulation output configuration, the digital input of 7fff provides a full -scale output, the 8000H output is given, and the 0000h provides a semi -standard output.
Internal reference
DAC715 contains+10V reference voltage. The reference output can be used to drive the external load, and the source current is as high as 2mA. The load current should be constant, otherwise the gain of the converter will change.
Output voltage
The output range of the output amplifier of DAC715 is 0 to+10V. Provide+0.4V or higher voltage.
FIG The relationship between adjustment. First adjust the offset to avoid the interaction of adjustment. See Table 1 with calibration values and code. The minimum range of these adjustments is ± 0.3%.
Disposal adjustment
The digital input code generated to generate zero output voltage was applied, and the offset potential meter or offset adjustment was adjusted to 0V.
gain adjustment
The application provides digital input with a maximum positive voltage output. Adjust the gain potential or gain adjustment D/A converter to obtain the full standard voltage.
Installation
General precautions
Due to the high precision of DAC715, system design problems such as grounding and contact resistance have become very important. The 1LSB value of 16 -bit converter with a 10V full -scale range is 152 μV. When the load current is 5mA, the series and connectors are only 60m , which will cause a voltage drop of 300 μV. To understand the meaning of the system layout, the resistance of a typical 1 ounce copper -printed circuit board is 1/2 m /square. For a 5mA load, a 10 mm wide 60 mm -length printed circuit conductor will cause a voltage drop of 150 μV.
The simulation output of DAC715 has a LSB size of 152 μV (–96DB). Within the frequency range of interest, the lower limit of the d/a must be kept below the level. DAC715's noise spectrum density (including noise generated by internal benchmarks) is shown in the typical performance curve.
The wiring connected to a high -resolution D/A converter should provide the best isolation with the RFI and EMI source. The key to eliminating radio frequency radiation or pickup is the small circuit area. The signal cables and their loop wires should be kept together so that they can have a small capture section for any external magnetic field. It is not recommended to use a steel wire wound structure.
Power and reference connection
The power supply decoupled capacitor should be added, as shown in Figure 4. Use 1 under --vcc 1To 10 μF 钽 Capacitors can get the best performance. Applications with a short critical settlement time can use 0.01 μF and AT+VCC as –vcc as under -vcc. The capacitor should be close to the packaging.
DAC715 has a separate simulation public pipe foot and digital public pipe foot. The current through DCOM is mainly switching transient, and the highest amplitude can reach 1mA. For all code, the current of ACOM is usually 5 μA.
Use separate simulation and digital grounding planes and single interconnection points to minimize the grounding circuit. Simulation feet are adjacent to each other, helping to isolate the analog signal from digital signals. The analog signal should stay away from the digital signal as much as possible and cross the right angle. The surrounding of D/A and the solid -state simulation ground plane near the simulation and power pins will be isolated D/A and switching current. It is recommended to connect DCOM and ACOM directly to the ground floor.
If multiple DAC715 is used, or if DAC715 is shared with other components, connect the ACOM and DCOM lines together once (instead of on each chip) to get better results.
Load connection
Since the reference point of VOUT and VREF OUT is ACOM pins, it is important to connect the D/A converter load directly to the ACOM pin. Reference Figure 5.
Drivers resistance and contact resistance are represented by R1 to R3. As long as the load resistance RL is constant, the R1 will only introduce the gain error, and it can be calibrated through the D/A gain adjustment or the system range gain. If the output voltage is detected on ACOM, R2 is part of RL.
In some applications, it is impractical to return the load to the ACOM pins of the D/A converter. The output voltage of the inductive system is reasonable, because as long as the R3 is a low -resistance layer or conductor, the DAC715 ACOM current has not changed. In this case, you may want to connect DCOM to the system to ground.
gain and offset adjustment connection potential meter
gain and offset adjustment pins provides fine -tuning using external potential meters. The 15 -circle potential provision provides sufficient resolution. These fine -tuning adjustments are ± 0.3%of the full scale range. Reference Figure 6.
The gain adjustment and offset adjustment circuit of DAC715 with D/A converter
DAC715 has been arranged so that these points can be easily driven by the external D/A converter. Reference Figure 7.12 D/A converter provides offset adjustment resolution and gain adjustment resolution, and step by step 30 μV to 50 μV per LSB.
When the output of the D/A converter is about 0 volume, the nominal value of the gain and offset appears.
Digital interface
Bus interface
DAC715 has a 16 -bit dual cushioning data interface and control line, which is convenient to connect to 16 -bit bus.Dual buffer characteristics allow multiple D/A to be updated at the same time.
A0 is the enable control control of the data input lock.A1 is the opening of D/A lock.WR is used to select data into locks enabled by A0 and A1.Refer to the box diagram of FIG. 1 and the timing diagram of page 3.
CLR sets the input data lock and D/A locks to 0000h (D/A output as 5V).
Single buffer operation
In order to operate the DAC715 interface as a buffer lock, the data input lock memory is permanently used by connecting A0 to DCOM.If A1 is not required to enable D/A, it should also be connected to DCOM.For this working mode, the width of the WR requires at least 80ns in order to pass the data into the D/A lock in the data input to the D/A.
Transparent interface
The digital interface of DAC715 can be transparent by asserting AO, A1, and WR, and high CLR.
