Features

Broadband: 1000MHz

High conversion rate: 8000V/μs

Flexible supply range: [[[[[[[ 123]

± 1.4V to ± 6.3V dual power supply

+2.8V to+12.6V single power supply

output current: 60mA (continuous)

[

[ 123] Peak output current: 350ma

Low static current: 5.8ma

Low static current: 5.8ma

#8226; Optional intermediate power reference buffer

Application

Low impedance reference buffer

] Video/Radio Equipment

Communication equipment

High -speed data collection

Test equipment and instruments [123 123 ]

Explanation

BUF602

is a closed -loop buffer, which is recommended to be widely used. Its broad band width (1000MHz) and high conversion rate (8000V/μs) make it an ideal choice for cushioning very high -frequency signals. For AC coupling applications, an optional mid -point reference (VREF) is provided to reduce the number of external components required and provide the necessary power current required for the reference.

BUF602 has a standard SO-8 surface paste packaging and SOT23-5, which requires a smaller area.

Typical features: vs ± 5V

ta +25 ° C and rl 100

Application information Broadband buffer operation BUF602 provides excellent communication performance of broadband buffer. Only a static current of 5.8mA is required. The BUF602 will swing to the 1V range of any power rail and provide a current of more than 60mA at room temperature. This low -output cleanliness requirement, plus partial voltage independent of the power supply voltage, provides a significant single (+5V) power operation. BUF602 will provide bandwidth greater than 500MHz, and drives 2VPP output to 100 on a single+5V power supply.

FIG5V electrical characteristics and typical characteristic foundation DC coupling pair dual -power supply circuit configuration. For the purpose of testing, the input impedance is used to set the input impedance to 50 , and the output impedance is used to set the output impedance to 50 The voltage fluctuation reported in the specification is obtained directly at the input and output pin, while the load power (DBM) is defined under the matching 50 In addition to the usual power supply container, a 0.01 μF capacitor may also be included between the two power pins. This optional additional capacitor usually improves the second harmonic distortion of 3DB to 6DB.

FIG. 32 shows the configuration of AC Coupling Couplet Power Circuit for+5V electrical and typical characteristics. Although it is not the design of a railway to the railway, the BUF602 requires the smallest input and output voltage to be cleaned than other very wide -frequency band buffer. It will provide a 3VPP output amplitude on a single+5V power supply, with a bandwidth of greater than 400MHz. The key requirement of the BUF602 broadband single power supply is to keep the output signal swing within the available voltage range. The circuit in FIG. 32 uses the internal midpoint benchmark to establish the input midpoint bias. Then enter the signal to be coupled to the midpoint voltage bias. Similarly, on a single+5V power supply, the output voltage can swing within the 1V range of any one power supply, while providing an output current of more than 60mA. A load that requires a 100Ω in this characteristic circuit to a midpoint bias.

Low -impedance transmission line

The most important equation and the technical foundation of the transmission lines support the results of various driving circuits introduced here. The ideal zero -ohm impedance transmission medium, its inductance and capacitors are distributed on the transmission cable. The inductance and capacitance will reduce the quality of the line. Each input is connected to the line through the chrysanthemum chain or ring road, and each input end adds at least a few pickup antenna capacitors. Typical transmission line impedance (ZO) defines the line type. In Formula 1, the impedance is calculated by the line capacitor (CT) of the line inductance (LT):

Similar As shown in equivalent 2:

For symmetrical records, the typical value of ZO is 240 the typical value of the coaxial cable is 75 or 50 #8486;. For the bus line on the printing circuit board (PCB), in the high data rate bus system, ZO sometimes reduces to 30 to 40 #8486. Generally speaking, the more complicated the bus system, the lower the ZO. Because it increases the capacitance of the transmission medium, a complex system reduces typical line impedance, thereby putting forward higher drivers for the line drives used here.

The transmission line is always connected to the transmitting end, and the end is always connected to the receiver end. The unrefined line will generate signal reflexes to reduce pulse preservation. Drive circuit transmits output voltage (VOUT) through the line. The signal appears at the end of the line, and it will be reflected when it is not terminated. VOUT's reflection part is called VREFL, which returns to the driver. The transmitting signal is the sum of the original signal VOUT and reflective VREFL.

The size of the reflected signal depends on the value of the typical line impedance (ZO) and the terminal resistance Z1.

γ represents the reflection coefficient, described by the formula 5.

The range of γ is -1 to +1.

The conditions at the 5th corner of the equation are as follows:

The unconnected driving circuit makes the situation more complicated. VREFL reflected on the side of the driver for the second time, wandering back and forth on the line like table tennis. When this happens, it is usually impossible to restore the output signal Vout on the receiver side.

The figure shown in FIG. 33 uses BUF602 as a line drive. The BUF602 has high input impedance and low output impedance, so it is an ideal choice no matter when the buffer is required.

Self -biased pressure, low impedance intermediate power supply voltage benchmark

combined with the BUF602 with BUF602, which can create a low impedance benchmark from DC to 250MHz Essence

FIG. 34 uses 0.1 μF external capacitors to filter noise.

For reference, AC coupling broadband buffer

No matter when you need a high -speed AC coupling buffer, you should consider BUF602. One feature of the BUF602 is to provide intermediate reference voltage and save external components and power consumption. It is recommended to install a capacitor at the benchmark output terminal in the middle to limit the noise contribution of the intermediate power reference voltage generated by two 50K internal resistors.

Design Tools

Demonstration fixed device

There are two printing circuit boards (PCB) that can be used to assist the use of BUF602 in the two packaging options to conduct a preliminary assessment of the circuit performance in its two packaging options. Essence Both products are free offered polychloribobenes provided free of charge, and they are attached with user guides. The summary information of these fixed devices is shown in Table 1.

You can obtain a demonstration device on the website of Texas Instrument Company through the BUF602 product folder.

Macro model and application support

When analyzing the performance of the simulation circuit and system, use itSPICE's computer simulation of circuit performance is very useful. This is especially true for video and RF amplifier circuits, because parasitic capacitors and inductors will have a significant impact on circuit performance. You can obtain the BUF602 SPICE model (website) through the Ti website. These models can well predict small signal communication and transient performance under various operating conditions. They do not do well in predicting harmonic distortion or DG/DP characteristics. These models do not try to distinguish the packaging type in their small signal communication performance.

Output current and voltage

The output voltage and current capacity provided by BUF602 are usually not in the broadband buffer. Under the air load conditions of+25 ° C, the output voltage is usually less than 1.2V compared to any power rail; the swing of+25 ° C is limited to the 1.2V range of any power rail. In 15 load (minimum test load), the output of its output exceeds ± 60 mAh.

Although the above specifications are familiar with the industry, voltage and current restrictions are considered. In many applications, it is a voltage × current or V-I product, which is more related to the circuit operation. Refer to the buffer output voltage and current limit diagram in the typical feature (Figure 16). The X and Y axis of this figure show the zero voltage output current limit and zero current output voltage limit, respectively. The four quadrant gives a more detailed view of the BUF602 output drive capability. It notices that the figure is bound to the security operation area of u200bu200bthe largest internal power consumption of 1W. The resistance lines of the resistance are superimposed on the curve chart that the buf602 can drive ± 3V to 25 or ± 3.5V to 50 .

The minimum output voltage and current excess temperature are simulated at the worst situation at the worst case. Only when the cold starts, the output current and voltage will be reduced to the value shown in the electrical characteristic table. When the output transistor provides power, the knot temperature will increase, reducing the VBE (increasing the available output voltage swing) and increasing the current gain (increase the available output current). In the steady -state operation, because the output stage temperature will be higher than the lowest working environment temperature, the output voltage and current can always be greater than the value shown in the ultra -temperature specification.

For the buffer, the noise model is shown in Figure 35. Formula 6 shows the general form of the output noise voltage, as shown in Figure 35.

Heat analysis

Under extreme working conditions, the forced ventilation or high power operation of the Bu602 may be required. The maximum expectation will set the maximum allowable internal power consumption as described below. In any case, the highest knot temperature must not exceed 150 ° C.

The working knot temperature (TJ) is given by TA+PD θJa. Total internal power consumption (PD) is static power (PDQ) and losingThe sum of the additional power consumed by the level (PDL). Static power is the specified air supply current multiplication by the total power supply voltage of the entire component. PDL will depend on the required output signals and loads, but for the ground resistance load, when the output is fixed at 1/2 of the power supply voltage (for equivalent bipolar power supply), the PDL will be maximized. In this case, pdl vs2/(4 × rl).

Note that the internal power consumption is the power of the output level rather than the load.

As the worst case, use BUF602idBV in the homepage circuit to calculate the maximum TJ in the case of the highest specified environmental temperature+85 ° C and drive the ground 20

The maximum TJ +85 ° C+(0.37w × 150 ° C/W) 141 ° C.

Although this is still lower than the prescribed highest knot temperature, it may require lower test temperature for system reliability considerations. If the load requirements are forced to input the output of the positive output voltage or the current from the negative output end, the highest internal loss may occur. This allows high current through a large internal voltage drop in the output transistor. The output V-I chart (Figure 16) displayed in the typical feature includes the boundary of 1W of the largest internal power consumption under these conditions.

Circuit plate layout guide

To achieve the best performance and high -frequency amplifier, such as BUF602 requires careful attention to the plate layout parasites and external component types. Suggestions for optimization include:

a), minimize the parasitic capacitance of all signal input/output pins to any communication to the minimum. The parasitic capacitance on the output tube will cause unstable: at the irreversible input terminal, the parasitic capacitor will react with the source impedance, resulting in unintentional bandwidth limit. In order to reduce unnecessary capacitors, a window should be opened on all the ground and power plane around the signal I/O pins. Otherwise, the ground and power aircraft should remain complete elsewhere.

B), shortening distance ( lt; 0.25 "") from power pins to high -frequency 0.1 μF decoupling capacitors. At the device pin, the ground layout of grounding and power supply should not be close to the signal input/output pin pin pin pin pin pin pin pin pin pin pin absorbing pin . Avoid narrow power and ground traces to minimize the inductance between the pins and the decoupling capacitors. The power connection should always be disconnected with these capacitors. The optional power supply capacitor (0.1 μF) between the two power supply (0.1 μF) should be (For bipolar operation) will improve the second harmonic distortion performance. The main power supply should also use a larger (2.2 μF to 6.8 μF) decoupling capacitor, which is valid at a lower frequency. These can be placed at departure at departure. Where the device is slightly far away, and can be shared between multiple devices in the same area of u200bu200bPCB.

C), carefully selection and placing the external component will maintain the high -frequency performance of the BUF602. Low electric anti -electricitytype. Surface stickers are the best work and allow more compact overall layout. The metal film or carbon ingredients, axial binding resistance can also provide good high -frequency performance. Similarly, keep their lead and PCB traces as short as possible. Do not use a wire winding resistor in high -frequency applications.

D), the connection to other broadband devices on the board can be performed through short, direct paths or through the board transmission line. For short connections, the input of tracking and to the next device is considered as a concentrated capacitor load. A relatively wide trace line (50 to 100 mils) should be used, and it is best to open the ground and power aircraft around it. If a long record is required, and the inherent 6DB signal loss of the double -end transmission line is acceptable, the use of micro -band lines or strip line technology to match the impedance transmission line (see the relevant micro -band and strap line layout technology ECL design manual). 50 environment does not need to be on the ship. In fact, a higher impedance environment will improve distortion, such as distortion and load charts.

E), it is not recommended to put high -speed parts such as buf602. The additional lead length introduced by the socket and a very troublesome parasitic network for needle capacitors will be almost impossible to achieve smooth and stable frequency response. Welded BUF602 to the circuit board to get the best results.

Input and ESD protection

BUF602 is built on a very high -speed complementary bipolar process. For these very small geometric devices, the internal cutting voltage is relatively low. These segments are reflected in the absolute maximum rating table. As shown in Figure 36, all device pins are protected by the internal ESD to protect the power supply.

These diode provides moderate protection to enter an over -drive voltage higher than the power supply. Protecting diode can usually support 30mA continuous current. If there may be a higher current (for example, in a system with a ± 15V power component to the BUF602), adding a string -limited connected resistor should be added to the two input terminals. Keep these resistance as low as possible because high value will reduce noise performance and frequency response.