Features

■ Real-time clock records a few seconds in BCD format

b : 5-v operation

-BQ4802LY: 3.3-V Operation

■ The battery switching circuit on the external SRAM, with non-easy loss of control

■ Back-up mode The next clock working current is less than 500 mAh

■ Micro -processor reset with the buttons super control

■ Independent independent time -effective timeout Look at the Dog fixed device

■ Power failure interruption warning

■

The programmable clock alarm interrupt activation in the spare battery mode [ [ 123]

■

Periodic programmable interruption

■

Low battery battery warning ■

28 -pin SOIC, TSSOP, and Snaphat package option

Application

■

■ Server

■ [ 123] Handheld data collection equipment

■ Medical equipment

■ Handheld instrument

■

Test test Equipment Instructions

BQ4802Y/BQ4802ly real time clock is a low -power micro -processor peripheral equipment, which integrates day clock, century -based calendar and CPU manager. 28-needle SoIC, Tssop or Snaphat, requires BQ48SH-28X6 to complete two-piece modules. BQ4802Y/BQ4802ly is an ideal choice for fax machines, copies, industrial control systems, sales points terminals, data recorders and computers. Typical application

BQ4802Y/BQ4802ly provides direct connection with 32.768 kHz quartz crystals and 3V spare batteries. By using conditional chips to enable the output (CEOUT) and battery voltage output (VOUT) pin, BQ4802Y/BQ4802LE can write protection and make non -loss external SRAM. The spare unit is powered on the real time clock, and SRAM information is maintained without system voltage. Crystals and batteries are included in modules to achieve more integrated solutions.

BQ4802Y/BQ4802ly contains a temperature compensation reference and comparator circuit for monitoring the status of its voltage supply. When the BQ4802y/BQ4802ly detects the situation, it will generate an interrupted warning, and then the microprocessor is reset. After the VCC rises to the allowable range, the reset remains to activate 200 milliseconds to allow power supply and processor to stabilize. The reset function also allows external buttons to be super control.

Order information

(1), DW, PW, and DSH packaging can provide tapes and rolls. Add an R suffix (ie BQ4802ydWR) to the device type.

(2), DSH software package only provides tapes.

(3), the BQ48SH-28X6 should be ordered to complete the Snaphat module, and the part number of the 3.3-V and 5-V modules is the same.

Figure Figure

Figure 3 is the box diagram of BQ4802Y/BQ4802ly. The following sections describe the function operations of BQ4802Y/BQ4802ly, including clock interface, data retention mode, power -up reset time, and interrupting the door dog timer.

Reading loop sequence diagram

Writing cycle sequence diagram

Functional description

Clock memory interface

BQ4802Y/BQ4802ly has the same clock/calendar and control information interface as standard SRAM. To read and write these locations, users must place BQ4802Y/BQ4802ly in an appropriate mode and meet regular requirements. Reading mode

When OE (output enabled) is low and CS (chip selection) is low, the BQ4802y/BQ4802ly is in the read mode. The unique address of the four addresses defines which one of the 16 clocks/calendar bytes. BQ4802y/BQ4802ly enables valid data to be available at the internal data I/O pins of the TAA (address access time). Enter the signal stable at the last address and meet the access time of CS and OE (output enable). If the CS and OE access time are not met, the valid data is available after the chip selects the access time (TACS) or the output enabled access time (TOE).

CS and OE control the status of eight three -state data I/O signals. If the output is activated before TAA, the data cable will be driven to an uncertain state until TAA. If the address input is changed when the CS and OE keep the low position, the output data is in TOH (the output data maintains time) Keep it valid, but it is uncertain before the next access address.

Writing mode

Whenever WE and CS are in active state, BQ4802Y/BQ4802ly is in the writing mode. The beginning of the writing operation is referenced from the decrease of we or CS. Write the early ascending edge of WE or CS. The address must be maintained throughout the cycle. Otherwise, before starting another reading or writing cycle, you must return at least TWR2 from CS or return to TWR1 from We.

Before the end of the writing, the data in the middle must be effective TDW, and then it is still valid for TDH1 or TDH2. During the writing cycle, OE should be kept at a high level to avoid the use of the bus; although if the output bus is activated by the low level of CS and OE, then after we fall, Low On We will disable output TWZ.

Reading Clock

Every second, the clock/calendar position that the user can access will be updated at the same time from the internal real -time counter. To prevent reading data during the conversion process, the BQ4802Y/BQ4802ly clock register should be stopped. Stop the update by setting up the update transmission (UTI) bit D3 of the control register E. As long as the UTI bit is 1, it is forbidden to update the user's access to the clock position. Once you read the appropriate clock memory position to retrieve the frozen clock information, the UTI bit should be reset to 0 to allow updates from the internal counter. Since the internal counter is not suspended by setting the UTI position, reading the clock position has no effect on the clock accuracy. Once the UTI bit is reset to 0, the internal register updates the user accessable register at the right time within a second. The suspension command issued during the clock update allows updates before frozen data.

Set clock

UTI bit must also be used to set BQ4802y/BQ4802ly clock. Once you set it, you can write the required information in the BCD format. Subtracting the UTI bit to 0 will transmit the written value to the internal clock countmaker and allow the update of the user's access to the register in one second.

Stop and start the clock oscillator

BQ4802y/BQ4802ly Clock is programmable to turn off when the component enters the spare battery mode. The method is to stop setting to 0 before power off. If the circuit board of BQ4802Y/BQ4802ly is used for a long time in the memory, you can use the stop bit to retain some battery capacity. When VCC drops below VSO, STOP is set to 1 to keep the clock run. When VCC is greater than VSO, no matter what the state is stopped, the BQ4802Y/BQ4802ly clock will run.

Power off/power -on loop

BQ4802Y/BQ4802LY continuously monitor whether the VCC is beyond the tolerance. During the power failure, when VCC is lower than VPFD, BQ4802Y/BQ4802ly writes a protective clock and a storage register. When VCC is less than VPFD u200bu200band BC is larger than PFD, or when VCC is smaller than VBC and VBC is less than VPFD, the power is switched to BC. RTC operation and storage data are maintained by effective spare energy. When VCC is higher than VPFD, the power supply is VCC. After VCC rises above VPFD, the writing protection will continue TCSR time.

The external CMOS static RAM is supported by the battery and uses VOUT and chip from BQ4802Y/BQ4802ly to enable the output pins. When the voltage input VCC decreases during the power failure, the chip enable and output CEOUT is forced to discontinue, independent of the chip enable input CEIN.

When VCC is lower than VPFD, this event is unconditionally written to protect the external SRAM. If the memory access is being conducted on the external SRAM during the power failure detection, the memory cycle will continue to be completed before the memory is written. If the memory cycle is not terminated within TWPT, the chip enables the output to output high -level high -level driving, and protects the control SRAM.

When the power supply continues to via VPFD, the internal switching device converts VOUT into external reserve energy. CEOUT is raised by VOUT energy.

During the power -powered period, when the VCC was higher than the input voltage source of the spare unit, Vout switched back to the main power supply. If the vpfd u0026 lt; VBC on the BQ4802y/BQ4802ly, switch to the main power at VPFD. After the power supply reaches VPFD, the CEOUT time to maintain a non -activity state TCER (up to 200 milliseconds), which has nothing to do with the CEIN input to allow the processor to stabilize.

During the effective operation of the power, the CEIN input was output with CEOUT with a delay of less than 12ns. Figure 2 shows the hardware connection of external RAM, battery and Crystal.

Provide a main backup energy input on BQ4802Y/BQ4802ly. BC input accepts a 3V main battery, usually a certain lithium chemical. Because the BQ4802y/BQ4802ly provides the reverse charging protection of the battery, the diode or the current limit resistance is required to connect with the battery. When there is no valid data to retain, in order to prevent the battery from exhausting, VOUT and CEOUT are quarantine battery inside the BC through the initial connection of A. Following the first application of VCC on VPFD, this isolation is broken, and the spare unit is powered by the VOUT and CEOUT of the external SRAM. The crystal should be as close to X1 and X2 as much as possible, and complies with the specifications of the electrical characteristic surface crystal specifications. Use the specified crystal, BQ4802Y/BQ4802ly RTC every month at room temperatureIt is within 1 minute. In the case of no crystal, a 32.768-kHz waveform can enter X1 with X2 ground ground. Power and crystals are integrated in the Snaphat module.

Powering and reset

BQ4802y/BQ4802ly provides power -on reset function. After VCC via VPFD, the RST pin will be pulled down and keeps low at the time when power is powered on. Under the valid battery voltage on BC, RST is still valid for VCC u003d VSS.

button reset

When the device is not in the reset cycle, the BQ4802y/BQ4802ly also provides a button super control reset. When the RST pin is released after being pulled down 1 μs, RST maintains 200 ms (typical) at a low level.

Looking at the Dog Turnion

Watch the door dog surveillance microprocessor activity by watching the door dog input (WDI). To use the door -to -door dog function, connect WDI to the bus or microprocessor I/O line. If the WDI keeps high or low time exceeding the timeout time (defaults to 1.5 seconds), BQ4802Y/BQ4802ly will assert WDO and RST.

Look at the door dog input

If you watch the door dog input (WDI) during the watch dog (from high to low, from low or minimum 100 -nanny pulse), BQ4802Y/BQ4802ly reset the door dog timer. The time to watch the door is set up by WD0 -WD2 in register B. BQ4802Y/BQ4802ly maintains the time -to -door dog timing programming through power circulation. The default status of WD0 -WD2 (no effective battery power) is 000 or 1.5 seconds when power is powered. Table 3 shows the timeout of the programmable door. After resetting the door, the timeout time is equal to programming dogs.

To disable the function of watching the door, please keep WDI floating. The internal resistance network (100-k u0026#8486; equivalent impedance at WDI) bias WDI to about 1.6 V. The internal comparator detects the level and disables the scheduled timer. When V is lower than the power failure threshold, the BQ4802Y/BQ4802ly will disable the function of watching dogs and disconnect WDI from its internal resistance network, so that it has high impedance.

Looking at the Dog Output

If there is a conversion or pulse at the WDI at the time of watching the door, the door dog output (WDO) will remain high. When the VCC is lower than the power failure threshold, enables the battery spare mode, or the WDI opening road, the BQ4802Y/BQ4802LE disables the door dog function, WDO is a logical high level. In the watch dog mode, if the WDI has not changed during the time of watching the door, the BQ4802Y/BQ4802ly will re -assertion to the T1 of the reset time. WDO becomes lower and in WDI keeps low before the next conversion. If WDI keeps high or low, RST generates a pulse (T1 second width) every 3 seconds. Figure 11 shows the timing of watching dogs.

Interrupt

BQ4802Y/BQ4802L ask. These three interrupt events are:

*periodic interrupt, which can be programmed from 30.5 μs to 500 ms.

*Alarm interruption, programmable to once every second to once.

*Power failure is interrupted, which can be enabled by the BQ4802y/BQ4802LY detection of the power failure.

A separate interrupt enable bit in the register C (interrupt register) enables the cycle, alarm and power failure interrupt. When an event occurs, it is set in the event logo in the logo register register D. If the corresponding event enlightenment is also set, a interrupt request is generated. Read the logo register to remove all the logo and make the INT high impedance. To reset the logo register, the BQ4802Y/BQ4802LA address must be kept stable at least 50 nan seconds in the register D to avoid accidental resetting.

Periodic interruption

The bit RS3 -RS0 programming periodic interrupt rate in the interrupt register. Users can interpret interruptions in two ways, or inquire or make PIE through the PIE to make the cycle logo in BQ4802Y/BQ4802ly. Read the logo register to reset the PF bit and return the int to high impedance. Table 5 shows the cycle rate.

Alarm interruption

The register 1, 3, 5, and 7 pairs of real clock alarm. In each update cycle, BQ4802Y/BQ4802ly compares the date, hours, minutes, and seconds of the clock register with the corresponding alarm register. If a corresponding logo is found in the register, all AF flags are matched. If the alarm interrupt is used to use AIE, the interrupt request is to remove the alarm conditions by reading the logo register. ALM1 Mem0 is shielded in the alarm register in the alarm register. Set Alm1 (D7) and ALM0 (D6) to 1 to block the alarm byte. According to Table 6, the alarm byte shielding can be used to select the frequency of alarm interrupt. When the BQ4802y/BQ4802ly is in the battery backup mode, the alarm interrupt can be activated by setting ABE in the interrupt register.

Under normal circumstances, the int pin will have high impedance backup during the battery. In the case of setting ABE, if the alarm conditions occur and set the AIEBit, the INT is driven to a low level.

Power-failure interruption

When VCC drops to the power failure detection point, set the power failure logo PWRF. If the power failure is also set up (PWRIE), the INT is low. The power failure interruption occurred before the BQ4802Y/BQ4802ly generated and reset and canceled the choice.

Low battery power warning

BQ4802Y/BQ4802ly Check the battery while powering. When the battery voltage is about 2.1 V, the battery valid logo BVF in the logo register is set to 0, indicating that the clock and RAM data may be invalid.

Mechanical Data

Note: A. All linear size units are inch (millimeters).

B. This drawing will not be notified separately if there is any change.

C. The main size does not include mold flying or protruding objects with no more than 0.006 (0.15).

D. It belongs to Jedec MS-013.

Note: A. All linear size units are millimeters.

B. This drawing will not be notified separately if there is any change.

C. The main size does not include mold flying or protruding objects with no more than 0.15.

D. It belongs to Jedec Mo-153.

Note: A. All linear size units are millimeters.

B. This drawing will not be notified separately if there is any change.