Feature

■ Standard digital audio interface receiver (EIAJ1201)

■ Sample rate: 32/44.1/48/88.2/88.2/88.2/88.2/88.2/88.2/88.2/88.2/88.2/88.2/88.2/88.2/88.2/88.2/88.2/88.2/88.2 96 kHz

■ Restore 128/256/384/512 FS system clock

■ Very low jitter system clock output (usually 80PS is 80ps )

■ The main clock oscillator on the film, only the external 12.000 MHz or 16.000 MHz crystal

■ optional PCM audio data format [ 123]

■

Use block to start signal output user position data, logo signal and channel status data ■

Single power+3.3V power supply

[ 123] ■

Packaging: 28 ssop

Application

AV receiver

■ md md Player

■ DAC unit

Instructions DIR1701

is a digital audio interface receiver (DIR), it, it, it Based on AES/EBU, IEC958, S/PDIF, and EIAJCP340/1201 consumer and professional format interface standards receiving and decoding audio data with a decoding up to 96 kHz. DIR1701 directly uses the channel status and user position to directly use it to the serial output pins, and provides a dedicated output pin for the most important channel status position.

The significant advantage of DIR1701 is that it has a 96 kHz sampling rate and the low -jitter recovery of the system implemented by the adaptive control tracking (spact #63722;). The input signal reintegrates the adaptive control tracking system and the patent sampling cycle to obtain the maximum quality. These two functions are necessary for the latest consumer and professional audio equipment. Among them, DIR has an interface to any type of Delta-Sigma ADC/DAC with a sampling rate of 96kHz.

block figure

Basic operational theory

DIR1701 has two PLL, PLL1 and PLL2. Spact (Sampling Period Adaptive Controlled Tracking) system is a newly developed clock recovery structure. It can from S/PDGet a very low clock jitter in the IF data input. DIR1701 requires a system clock to input to operate spact; internal PLL1 provides 100 MHz execution clocks. The system clock can be obtained by connecting appropriate crystal resonators on the XTI/XTO pin or input external clock input on the XTI pin, as shown in Figure 1. The internal PLL2 uses the output signal of the SPACT frequency estimation to generate the system clock SCKO.

When the S/PDIF input signal stops, SCKO maintains the latest tracking frequency. In addition, DIR1701 unlocked the unlocking state by unlocking the high -level output instructions of the pin. When the S/PDIF signal is restarted, the PLL is locked at about 1ms with a very low jitter with a very low jitter. DIR1701 is then locked by unlocking the low level output indicator of the pin. In this state, the Brate's foot indicates the actual bit rate of entering the S/PDIF signal.

The main function of the system clock output

DIR1701 is to restore audio data and low shake clocks from digital audio transmission lines. The clock that can be generated is SCKO (128/256/384/512FS, as shown in Table 1), BCKO (64FS), and LRCKO (1FS). SCKO is the output of the pressure -controlled oscillator (VCO) in the analog loop. The loop of the phase lock is composed of voltage control oscillator, phase and frequency detector, and external second -order circuit filter. The closed -loop transmission function specifies the PLL jitter attenuation characteristics, as shown in Figure 2.

By connecting BRSEL pins to one of the output pins shown in Table 2, one of the output pin BFRAME or CSBIT is defined to define the crystal frequency of the internal PLL. 12MHz crystal resonant can be used for 128FS (CSBIT), 256FS (open) and 384FS (BFRAME). 512FS (BFRAME) uses a 16MHz crystal resonator. The system clock frequency can be set through the control data of SCF0 and SCF1 pins (as shown in Table 3); before application reset, the data must be stable.

Table 4 shows the state of the system and the status of the audio clock and logo. The system clock precision required for the crystal resonator or external clock is ± 500ppm.

SCKO timing Bit rate detection

By using the interval frequency estimator (instead of the S/PDIF channel status bit), the DIR1701 automatically detects the sampling rate of the input S/PDIF signal and indicates the frequency of the Brate's tube foot.

Table 5 lists the frequency range of the report. In addition to 88.2 and 96 kHz, these sampling rates are with SThe channel status defined in the /PDIF specification is the same. When the Bit rate is 88.2 or 96 kHz, the indicator displays the same HL value. This state is not defined in the S/PDIF specification.

Locking the sequence specification of the runtime of the phase loop

Locking time

Audio data output timing and lock lock The relationship between the timing of the ring state indicator

When the analog PLL is still unlocked and the S/PDIF signal begins, after at least 10 rising edges, the S/PDIF decoder can detect the input S/PDIF signal. DOUT pin becomes lower (silent) until the mock lock ring is locked. The mute cycle Tint is less than 1ms (analog lock ring lock time is less than 0.5ms). When the decoder detects the input S/PDIF signal, UNLOCK becomes higher at the next LRCKO conversion. SCKO keeps its frequency at the latest tracking ratio.

When the S/PDIF signal does not exist after removal, the frequency of the DIR1701 Audio clock (SCKO, BCKO, LRCKO) is unknown.

Unlocking the minimum pulse width time

Case A PLL to unlock

High level, audio data output DOUT low (mute). The quiet cycle TUNL is at least 200 ms. During this period, the frequency of SCKO, BCKO and LRCKO maintains the latest tracking frequency.

If the S/PDIF signal is connected again within this unlock cycle, the bit rate will be changed to the input signal frequency after at least 1 millisecond (before the unlocking logo becomes low). CKTRNS pins indicate the effectiveness of SCKO. When CKTRNS is high, the frequency of SCKO, BCKO and LRCKO is in a conversion state between state.

When the incorrect verification error occurred B

When an error occurred in a sub -frame interval, unlocked during the child frame period Turned high, and then returned low at the next child frame.

During this strange sub -frame, the data output will save the previous data of each channel.

PCM audio interface

DIR1701 can generate 16 -bit or 24 -bit output data in the standard format and 24 -bit output data in IIS format.

Use format pins FMT1 and FMT0 to select the PCM audio interface format of DIR1701. Table 6 shows the FMT pin configuration.

Special output pins of professional and consumer applications

DIR1701 have parallel output pins, suitable for professional and consumer applications. In the professional mode, the time constant pre-worse to increase the sign of EMFLG for 50/15-μs. When the CSBIT byte 0 is high, the professional mode is set. When the 2nd to 4th bits of CSBIT byte 0 is 110, EMFLG becomes high. In other cases, EMFLG is low. Audio/non -audio logo ADFLG represents the S/PDIF data mode, the first place of the CSBIT byte 0. When ADFLG is low, S/PDIF data includes PCM audio signals. In other cases, Adflg is high.

In the consumer mode, EMFLG said 2 channel audio, pre-added time is 50/15-μs. When the CSBIT byte 0 is low, the consumer model is set. When the CSBIT byte 0 is 3 to 5, EMFLG becomes high. In other cases, EMFLG is low. Adflg signal indicates whether S/PDIF includes digital data, such as AC-3. When the CSBIT byte 0 is high, the S/PDIF transmitted includes non -audio signals. In other cases, ADFLG is low. These special output pins are only checked L-CH CS information. DIR1701 does not support the CRC inspection function under professional mode. As for other signs, the CS bits and user bits of professional and consumer applications are directly provided by CSBIT (pin 15) and URBIT (pin 16) serial mode. These needle feet indicate the sequence of L-CH and R-CH information.

The audio data and clock are regularly described as described below. When the corresponding child frame arrives, the serial output data begins after the 16 ± 8 BCKO clock. When B subframes arrive, BFRAME PIN becomes high during the 1/fs x 32 (s) period, and then BFRAME returns low after 32 frames.

Reservation order

DIR1701 needs to perform external reset operations after power calls. Figure 10 shows the sequence of reset after power -on. When the internal reset sequence is completed and the CKTRNS becomes low, DIR1701 has prepared to receive the S/PDIF signal. BFRAME, EMFLG, URBIT, and CSBIT pins are used for the configuration of the RST rising edge to the CKTRN decrease. When CKTRNS becomes lower, the S/PDIF signal is accepted. RST, TRST's minimum pulse width is 100ns. The RST delay after the power supply reaches 3V should be at least 10ms. When RST is low, all output pins except CKTRN and Unlock are low.

Typical circuit connection

C1, C2: Wingrser -packed container, 1 μF to 10 μF

C3, C4: Wingrsening container, 0.01 μF to 0.1 μF

C5, C6: OSC capacitor, 10 to 10 to 10 to33 PF

C7: Circular filter capacitor, 0.022 μF

C8: Platform capacitor, 0.0022 μF

R1: OSC resistor, 1 m #8486;

R2: Circle filter resistance, 6.8 k #8486; ++

Note: A. All linear size units are millimeters.

B. This drawing will not be notified separately if there is any change.

C. The main size does not include mold flying or protruding objects with no more than 0.15.

D. It belongs to Jedec MO-150.