General description

lm2641 is a dual -voltage power controller suitable for laptop and other battery power supply equipment. The fixed -frequency synchronous driving power MOSFET of the logic level N channel and the pulse jump mode of the ultra -high -efficiency power conversion in the range of 1000: 1 load current range. The pulse beating mode can be disabled, which is conducive to the fixed frequency operation regardless of the load current level. High DC gain current mode feedback control guarantees excellent lines and load adjustment and wide ring circuit bandwidth to respond to dynamic load quickly. The internal oscillator fix the switching frequency to 300 kg. Alternatively, the switch can be synchronized to the external clock and runs as high as 400 kg. Optional soft startup function restriction comes from entering the power supply and providing a simple method startup order. The logic level input allows the controller to open and close separately.

Main specifications

96%efficiency

5.5 to 30V input range

Dual output can be adjusted from 2.2 to 8V

0.5 %Typical load adjustment error

0.002%/V typical line adjustment error

Feature

300 kHz fixed frequency switch

Synchronization with external signals [ 123]

400 kilong

Optional jumping pulse mode

Two -time feedback

Input under pressure atresia

Output arrears of pressure stop Protection

Output over -stop protection

programmable soft start (each controller)

5V, 50 mA linear regulator output

2.5V Precision Output

28 -needle TSSOP

Application

Notebook and Subtylic Compute 123] Typical application circuit

Absolute maximum rated value (Note 2, (1)

in, SW1, and SW2 0.3 to 31V

FB1 and FB2 0.3 to 3V SD, open/level 1, open/level 2, 2ndfb/fpwm, synchronization, reference, SS1, SS2, components components 1. Components 2 and CSL1 0.3 to (vlin+0.3) v

Lin 0.3 to 6VCSH1, CSH2 and CSL2 (Note 12) 0.3 to 9VCBOOT1 to SW1 voltage From CBOOT2 to SW2 0.3 to 5V

Voltage from HDRV1 to SW1

from HDRV2 to SW2 0.3 volts

CBOOT1 to HDRV1 and CBOOT2

HDRV2 type 0.3 volts

Connect temperature. +150 degrees Celsius

Power Consumption (Note 3) 883 MW

Environmental storage temperature. (TJ) 65 to+150 ; C

Welding stay time, temperature. Note (4)

Waves 4 seconds, 260 degrees Celsius

Infrared 10 seconds, 240 degrees Celsius

Voic phase 75 seconds, 219 ; C

ESD rated value (Note 5) 2 KV

Rate the rated value (Note 1, 2)

vin 5.5 to 30V

Connect temperature. (TJ) 0 to+125 ; C

Electrical characteristics

The typical values and limits in ordinary fonts are suitable for TJ 25 ; C. The limit of the black body display is suitable for the entire operating joint temperature range, that is, 0 to+125 ; C. Unless there are other regulations in the parameters or conditions, VIN 10V, VSD Von/OFF1 Von/OFF2 5V (Note 2, 6, 7)

Electric Features (continued)

The typical values and limits in ordinary fonts are suitable for TJ 25 ; C. The limit of the black body display is suitable for the entire operating joint temperature range, that is, 0 to+125 ; C. Unless there are other regulations in the parameters or conditions, VIN 10V, VSD Von/OFF1 Von/OFF2 5V (Note 2, 6, 7)

Note 1: Unless there are other regulations, all voltages are related to the voltage on the GND and PGND pins.

Note 2: The absolute maximum rated value means that the device may be damaged when the limit is exceeded. The operating rated value refers to the guarantee of the device operation. Running rated values do not mean guarantee performance restrictions. For guarantee performance restrictions and related test conditions, please refer to the electrical characteristic table.

Note 3: The absolute maximum power consumption depends on the environmental temperature. The rated value of 883 MW is replaced by 150 ; C, 70 ; C and 90.6 ; C/W. θja, where PMAX is the absolute maximum power consumption, TJMAX is the absolute maximum power consumption, TA is the ambient temperature, and θJa is the thermal resistance of the pairing environment for packaging. θ90.6 θ represents the worst case of W/A28 needle TSSOP without heat dissipation. Heating can safely release more energy. Absolute maximum power consumption must be higher than 70 degrees Celsius, and the degree of Celsius is reduced by 11.04 MW per degree. LM2641 actively restricted its knot temperature to about 150 degrees Celsius.

Note 4: For more information on welding plastic small shape packaging, please refer to the packaging data manual provided by the National Semiconductor Corporation.

Note 5: For test purposes, use ESD with human models, and 100 PF capacitors discharge through 1.5 k resistors.

Note 6: The feature data center of TA TJ 25 ; C. Do not guarantee typical values.

Note 7: Guarantee all restrictions. All electrical characteristics with room temperature limit are tested in the production process with TA 25 ° C. All thermal and cold values are guaranteed by controlling electrical characteristics and processes and temperature changes and applying statistical processes.

Note 8: Both controller open, but not switch. Measure the current entering IC at the IN, CSL1, CSH1, CSL2, and CSH2. Enter the transformation of switching from 10V to 5V by 0.50 to the CSL1 and CSH1. The values of input at CSL2 and CSH2 are multiplied by 0.33 to simulate the effect of switch transformation from 10V to 3.3V. After multiplying, all five currents are added. Because the voltage of the CSL1 input end is greater than Lin to the VOUT switching threshold, most of the input power currents enter IC through CSL1.

Note 9: Two switch controllers are closed. 5V, 50 MA linear regulator (LIN output) and accuracy 2.5V reference (REF output) are kept open.

Note 10: The switch controller and 2.5V precision benchmark are closed. 5V, 50 mAh linear regulator keeps connecting.

Note 11: The controller is closed until the voltage of 5V and 50 MA linear regulators (lin output) reaches the threshold.

Note 12: In the application where the output voltage may exceed the absolute maximum rated value, 100 the resistor must be connected in series with the CSH and CSL.

Typical performance features

Operation theory

The basic operation of the current mode controller keeps the output voltage in the constant value control loop. LM2641 controller has two main operationsModel: Mes a pulse width modulation (FPWM), where the controller is always working at a fixed frequency, and the mode output load when the pulse jump controller is reduced to improve the light load efficiency.

FPWM working mode

Pull the FPWM pin and lower the boot operation mode as the compulsory pulse width modulation (FPWM). This means that LM2641 will always work at a fixed frequency, regardless of the output load. The operating cycle is: the high -side effect transistor switch is per clock cycle, so that the current flows over the sensor. This inductor current rises, causing the sensor resistance, which is an induction amplifier by the current. The voltage signal from the current detection amplifier is applied to the control level of the comparative error set settings with the input terminal of the PWM comparator. Once the water influenza signal reaches the control voltage, the PWM communication device resets off the high -voltage drive logic FET switch. The low -side FET switch is turned on after the delay time

The smaller of the following two:

(a) SW pins voltage reaches the time required (that is, the voltage is through the direct protection circuit from the direct protection circuit detect).

(B) 100 NS, this is the maximum delayed preset value. During the very light load (in FPWM mode), the electrochemicaler current must flow through the low -voltage field effect pipe switch in a negative direction to maintain a fixed frequency operation mode. Therefore, when the built -in zero cross -crossing is activated, the detector is disabled (that is, when the FPWM pin is pulled to a low state). It should be noted that if the FPWM pin is high (the operation is described in the next section), the excess detector will turn the low -side FET switch to zero at any time at any time (this can prevent the negative inductor current).

Pulse running method

Pulling the FPWM pin to high, which can make LM2641's pulse frequency jump mode under the negative load, of which the switching frequency decreases as the output load decreases. The controller will run in a fixed frequency mode, and if the output load current is high enough, the output load is high enough. Under the light load, the pulse skipping will cause higher efficiency, such as reducing the switching frequency will reduce the loss of switching. The load current value fixed frequency to the pulse frequency jump operation occurred as low as the power sensor current was low to cause the voltage measured by the current influenza response resistor (R4) or R13) below 25 millivolves. In the pulse skip mode, the high -side FET switch will rotate the voltage at the reference value voltage at the beginning of the feedback pin at the beginning of the first clock cycle. The high -voltage side FET switch is kept connected until the voltage on the current response resistor rises to 25 MV (and then shuts down).

Slope compensation

All current mode controllers need to use slope compensation to prevent secondary resonance. This compensation is built into LM2641. The internal compensation assumes that the RSENSE value is 25 m , the value of the inductor is 6.8 μH, and the maximum output voltage is 6V. In order to prevent oscillation, make upThe slope M slope must be equal to the voltage waveform at the output end of the current amplifier. The relationship between slope M and external components is as follows: mcomp mcs ampere (maximum value) n x rSense x vout (MAX)/lmcomp is the slope of the slope.

MCS AMP (MAX) is the voltage of the output end of the current detection amplifier. N is the gain of the current detection amplifier. RSENSE is the value of the current detection resistor. VOUT (MAX) is the maximum output voltage. L is an inductance of the output inductor. It should be noted that because the RSENSE value appears in the molecule and L is a denominator, these two values can increase or reduce the slope according to the same proportion. The higher the load current value, the lower the RSENSE value. The inductance value of the output sensor should reduce the same percentage to maintain the correct slope compensation.

Application information

Improved transient response

If the output voltage is lower than 97%of the nominal value, the low -voltage adjustment (LREG) comparator will start the high side field The logic of the effect of the transistor switch until the output returns to normal. The low -voltage field effect transistor switch was postponed during this period. This operation will improve the transient response because it bypass the error amplifier and PWM comparator, and force the high -pressure side to connect until the output returns to normal. The function of this period is disabled. A self -lifting capacitor of a ""flying"" high -voltage high -voltage side gate is used to generate the driving voltage of the gate for the high -voltage field effect transistor switch. This starting with a capacitor uses the internal as a low -voltage side FET switch. When the high -side effect transistor switch is turned on, the source is pulled up near the input voltage. By increasing the grid drive voltage by self -lifting capacitors to ensure that the grid drive voltage is at least compared with the source.

References

The internal band gap basis is used to generate a reference voltage of 2.5V connected to the REF pin. The guarantee tolerance of this reference voltage is ± 2%as long as the working temperature range is long ≤5 mAh. The REF pin does not require bypass electrical containers, but it can be used to reduce noise.

Application information (continued)

5V Lin output

LM2641 contains a built -in 5V/50 mAh LDO regulator, its output is connected to the lin pin. Since this is an LDO regulator, it needs an external capacitor to maintain stability. The stability of the minimum power capacity required is 4.7 μF, and ESR is within about 100 m range to 3 It is recommended that a high -quality solid pillar capacitor (not using ceramics due to the melting of electric slag). If a low temperature operation is required, the capacitor must choose the entire working temperature range application of ESR in a stable state. Because the current limitation of this LDO regulator is set at 85 mAh, it can be used for a load current of about 50 mAh (assuming that the total IC power consumption does not exceed the maximum value). With the entire working temperature range of the load, it is VLINThe worst situation value provides a guaranteed specification current as high as 25mA (see electrical characteristics). It is estimated that the VLIN output voltage is from ILIN 25ma to ILin 50mA. The change of VLIN is about the reasons of load (typical values). It is expected to be -30mV only, not guaranteed). Vlin decreases and increases load current. It must be understood that the maximum allowable current 50mA must include the current circuit consumed by the gate driver. This means that the use of the lin pin is 50 mAh in the internal use of any current in use for gates drivers. Each switch is used in the grid drive current to calculate the output using the following formulas: IGD 2xqxvosc

IGD is the gate -drive current provided by Vlin. Q is the selected grid charge required for the selected FET (see FET data table: grid charge characteristics). FOSC is the switch frequency. Example: As shown in typical applications, if FETNDS8410 is used with LM2641, LM2641 is the opening of the door voltage (VGS) to 5V V iodine 4.3V. Referring to the NDS8410 dataset, the curve grid charge characteristics indicate that the grid charge of this VGS value is about 24 NC. Assuming that the switching frequency is 300 kHz, the grid drive current used for each switch output is: IGD 2xqxvosc 2 x (24 x 10 9) x (3 x 105) 14.4 mia

] If both outputs are switches, the total grid drive current is drawn twice (28.8 mAh). Note that the voltage at the switch output#1 is 4.8V or higher, and the internal gate -drive current is obtained from the output (which means that the complete 50 mA can be used outside the lin pin outside). The basic operating frequency of synchronous pipe foot 300kHz can improve the use of synchronous pipe foots and external CMOS or TTL clocks. Synchronous pulses must have the minimum pulse width of 200 nan seconds. If the synchronization function is not used, the synchronous pins must be connected to the lin pin or ground to prevent errors from triggering

Flow limit circuit

LM2641 protected, and will not be due to the internal output current from one internal The current limit comparator, it monitors the output current cyclical. The voltage generated by the current limiter on the output sensor exceeds 100 mv (positive or negative). If the responding voltage exceeds 100 millivolttrasses, the high -voltage side effect transistor switch is turned off. If the responding voltage is lower than -100mV, the low-side FET switch is turned off. It should be noticed that the need for sufficient output current to activate the current limited circuit will cause the output voltage to decrease, which may cause the underwriting lock -up (see the next section).

Impurd voltage/overvoltage protection

LM2641 contains a protective circuit, if the output voltage is too low (UV) or too high (OV). If a UV or OV failure occurs, LM2641 will be locked at the high -edge field effect transistor.Closed, and the low -border effect transistor is closed and opened. If the output voltage is lower than 70%of the nominal value, the underwriter will lock LM2641. When recovery, the device must be turned off and then recovered. It should be noted that the voltage of the output of the UV lock in the excessive output current decreases. The ultraviolet locking circuit is started. If the output voltage exceeds 150%of the icon value, the over -voltage comparator locks LM2641. As mentioned earlier, the power must be turned off before opening the power to restore the operation. It must be noted that the OV 能 lock cannot protect the load from failing to damage when the load fails (FET short circuit and connect the input voltage to the load). When such a failure occurs, the load can be protected to use the fuse in the power cord. Since the OV locks are activated, the low -side FET switch will be turned on. If the FET and fuses are activated, the melting size of the tandem fuse melts is correct.

Soft start

The internal 5μA current source pins connected to the soft start of the soft start allowing the user to program LM2641. If the capacitor is connected to the SS pin, the voltage on the pin will increase linearly when connected. This voltage is used to control the pulse width switch of the crystal tube. The pulse width increases from a very narrow value to start linearly to the SS pin voltage 1.3V. At this time, the pulse to the pulse current limiter is controlled until the pulse width reaches the rated value (PWM current mode control loop is controlled). LM2641 contains a digital counter (reference oscillator frequency) by soft startup interval. The maximum SS time period of this distribution is the oscillator clock, which means that the time cycle is with the oscillator frequency: the maximum allowed SS interval 4096/fosc

Application information (continued)

If the output voltage The device will be locked during the number of 1%in the range of the nominal value, and the device will be locked. When recovery operation, the power supply must be switched from closed to opening. As the input voltage increases, the vein width switching field effects of the transistor are reduced as the input voltage increases. If the pulse width is less than 350ns, the pulse jitter may occur with a slightly different pulse width. This does not affect the stability of the regulator or the output voltage accuracy.

Starting problem

LM2641 contains an output under pressure protection, a circuit composed of a digital counter and a comparator monitoring VOUT. When booting, the counter starting work When the input voltage reaches about 3V, the clock cycle is calculated. If the counter reaching 4096 cycle output voltage to rise to 1%of the nominal value before the counter, the IC will be locked under the condition that the underwriter fails. The function of this protection is to close the overload of the regulator output (such as short circuit). However, if the locks cannot start the circuit, the fault design will be reasonable. The following two parts explain how to avoid these types of problems: the input voltage rises time, if the input voltage rises too slowly,LM2641 locks the lock -up state. In order to avoid this problem, the input voltage must be increased enough to enter the adjustment before the 4096 counting time interval. For 300 kHz switching frequency, 4096 cycles are completed within 13.6 milliseconds. In fact, the total rising time of the vehicle identification number should not be close to the 4096 clock cycle limit, if it is necessary to ensure reliable start. It needs to be noted that the total rise time of VIN will also be affected. When the power converter starts to switch, the voltage drops caused by the current load (absorbing the power from the input capacitor) Overview). It is also important that this type of startup problem is more likely to occur when the output voltage is higher, because the input voltage must rise to a higher voltage to adjust the output voltage (that is, the input DV/DT speed must be faster). The proposed output voltage limit should not exceed 6V.

Input capacitance

The number and type of input capacitor are directly related to the startup capabilities of the regulatory agency. The reason is that the input capacitor starts the power converter when switching as a regulator. Generally, the input voltage (that is, the input capacitor) will decrease as the power converter starts, which will cause the vehicle identification number (VIN) to decline. If the input capacitor is too small or the ESR is too large, the input volume may not be fast enough to allow the output voltage to count at 4096 cycles in the digital clock. To prevent such startup problems:

1. Input capacitors must provide sufficient volume capacity and low impedance. The solid cavels used for high -frequency switch applications are usually provided for the best cost/performance characteristics and low ESR, even at low temperature. Ceramic capacitors also have very low ESRs throughout the temperature, but the X5R/X7R electron type type should be used to ensure enough capacitors (Z5U or Y5F type is not suitable). Some newer electrolytic types, such as POSCAP, OSCON and polymer electrolyte can also be used as input capacitors. However, the application will increase significantly when the temperature is used as electric residue to melt at low temperature at the temperature lower than 0 ; C. Most aluminum electrolytes cannot be used with this IC at a temperature below this restriction. Check the ESR specifications of the selected capacitors if you need to operate at a low temperature, please do it carefully.

2. Input capacitors must physical positioning out of the switch over one centimeters away, and the tracking inductance as a tracker in the circuit diameter of the switching current will cause problems.

Circle compensation

LM2641 must be appropriately compensated to ensure stable operation and good transient response. The same control of the circuit as anyone is optimized when compensation is optimized, so as to maintain sufficient phase margin while obtaining the maximum bandwidth, thereby obtaining the best performance stability. The optimal performance of LM2641 is usually obtained in the following situations: the ring bandwidth (defined as the ring gain equal to the unit) in the range of FOSC/10 to FOSC/5Inside. When discussing the stability of the circuit, it should be noted that there is a high -frequency pole FP (HF), which can be approximately similar to: FP (HF) ～ fosc/2 x qs (assuming QS u0026 LT; 0.5)

It can be seen from the approximate values of QS that the frequency of the maximum FP (HF) appears at the maximum value of Vin. The minimum frequency of FP (HF) is FOSC/10 (when the vehicle recognition number is 4.5V and Vout 1.8V). As mentioned above, the position of the pole FP (HF) is usually from FOSC/10 to FOSC/4. This pole is usually near the cross frequency of unit gain. If compensation is not performed, the phase margin can be significantly reduced. Generally, ESR of the output capacitor forms a zero frequency that is very close to the FP (HF), and provides a negative phase to eliminate it. Therefore, you must choose the output capacitor carefully. Most of the LM2641's loop compensation is output from an error amplifier to the R-C network (see Figure 4). Because this is a cross -guide amplifier, it has a very high output impedance (160 k ).

The components displayed will add poles and zero gains to the loop by the following forms:

C10 plus a pole, the frequency is from the lower formula below formula Give:

fp (C10) 1/[2πx C10 (R11+160k)

C12 adds a pole, the frequency is given from the following formula:

fp (C12) 1/[2πx C12 (R11 | | 160K)

R11 plus a 0, the frequency is given from the following formula:

fz (r11) 1/[2πxxxxx R11 (C10+C12)

The output capacitor adds one pole and one zero: FP (COUT) 1/[2πx RL x Cout] fz (ESR) 1/[2πx ESR x Cout] type Among them, RL is a load resistance, and ESR is the series resistance of the equivalent value output capacitor. The function of the compensation component will be stated in the qualitative discussion of the typical circuit gain diagram. For LM2641 applications, as shown in Figure 5.

C10 and R11 to form poles and zero. The change value C10 moves pole point and zero -point frequency. Change R11 to move zero without significant impact. The C10 pole is usually called dominant pole. Its main function is to reduce the width of the loop and reduce the bandwidth. Some positive transitions need to be added with some positive transitions from the two. Without this zero, these two poles will cause the phase of 180 ; this is obviously unstable. Usually you will get the best results. If you choose R11, make FZ(R11) The frequency of (R11) is in the range of FC/4 to FC, where FC is the cross frequency of unit gain.

Output capacitor (together with load resistance RL)

to form a pole displayed as FP (COUT). Although the polar point changes with RL, the loop gain also changes proportional, which means that the consolidation frequency of the unit gain is basically constant, which is basically constant, which has nothing to do with the RL value. C12 is most commonly used to create additional poles to bypass compensation. In many applications, this capacitor is unnecessary. If you use C12, if the magnetic pole is set in the range of FOSC/2 to 2FOSC. This will provide a bypass of high -frequency noise switch but only a small amount of negative phase at the unit gain cross frequency. COUT's ESR (and COUT capacitors) forms zero FZ (ESR), usually in 10kHz and 50kHz. This zero is very important because it offsets the phase shift caused by high -frequency pole FP (HF). It is important to choose a COUT with the correct capacitor and ESR values, and place this zero point near FC (typical FC/2 to FC). As an example, we will analyze the 3.3V design drawing of the loop gain. The value used for calculation includes:

vin 12 volts

Voltage 3.3v@4a

COUT C14+C16 200 μF

ESR 60 m (each) 30 m Total

fosc 300kHz

fp (high frequency) ~ 40kHz

r13 20m

l2 6.8 μH

rl 0.825

DC gain 55db

The compensation component value is: C10

2200 PF, R11 8.2K, not using C12.使用这个数据，计算极点和零点：

fp（C10） 1/[2πX C10（R11+160k）] 430Hz

fz（R11） 1/[2πX R11（ C10+c12)] 8.8kHz

fp (COUT) 1/[2πx RL x Cout] 960Hz

fz (ESR) 1/[2πx ESR x Cout] 27kHz

fp (high frequency) ~ 40kHz

Use these values. The calculated gain chart is shown in Figure 6.

From the figure, it can be seen that the cross -gain crossing on the frequency FC is expected to be about 25kHz. Use this value, then calculate the phase of the pointAbout 84 ;. To verify the accuracy of these calculations, the circuit uses a network analyzer for table frame testing. The measurement of the measurement is shown in Figure 7.

The measured gain curve and predictive value measured are very close to values. At 0db, the phase of the phase is slightly less than the prediction value (71 ; vs.84 ;). This is because the negative transition contribution of the high -frequency magnetic pole is not included in this simplified analysis. It should be noted that the bandwidth of 25kHz 70 ; the phase of the phase is very good, which represents the best compensation for this group of values for VIN, VOUT, Electricity and RL

Optimized stability

[123 ] The best tool for measuring bandwidth and phase Margin is a network analyzer. If this is not available, a simple method of measuring the stability of the loop is to apply to the minimum to the maximum output load current jump and observe the output voltage generated by observing. The design has a good phase (u0026 gt; 50 ;) usually shows the ""No"" output voltage transient transient and return to its nominal value. It should be noted that stability (phase margin) does not require the best to stabilize the regulator. The analysis in the previous section was changed by changing R11 and C10 to deliberately reduce the phase of the phase of about 35 ; and re -testing the jump response. This output waveform shows a slight sound after the initial return to the nominal value, but it is completely stable in other cases. In most cases, the compensation component is displayed in a typical application circuit to provide good performance. To assist the optimization of phase margin, follow the following guidelines to show the effect of changing various components. COUT: Increasing the COUT capacitance will reduce the frequency of the pole FP (COUT) and reduce the circular bandwidth. If the loop bandwidth is too wide, increasing the COUT is beneficial (increasing phase margin) (u0026 gt; FOSC/5) to put the high frequency extremely near the unit gain frequency. COUT's ESR: ESR forms zero FZ (ESR), that is, the negative transition frequency near the unit gain needs to be eliminated. High ESR capacitors cannot be used because the frequency of zero is too low, which will cause the ring bandwidth to be too wide. R11/C10: They form a pole and one zero. The change of the change value C10 also changes the frequency of the pole and zero point at the same time. Note that this will cause the frequency of two extremes to move up and down from zero, and adjust the C10 on the ring bandwidth without significant effects. The value of the R11 will move zero FZ (R11), but it does not significantly change the C10 pole (because the value of the R11 is far less than 160k the output GM amplifier). Because only zero is moving, this will affect bandwidth and phase habits. This means that adjusting the R11 is a simple way to maximize the position provided by zero point. If FZ (R11) is generally obtained within the frequency range of FC/4 to FC, the best results are usually obtained (where FC is a cross -cross frequency of unit gain).

D