Features

single -chip digital audio interface receiver (DIR), including the low shake clock recovery system

IEC958), Jeita CPR-1205 (formerly EIAJ CP-1201, CP-340), AES3, EBU Tech3250

input signals from dual-phase input signals for clock recovery and data decoding, which is usually called S/ S/ usually called S/ S/ usually called S/ S/ usually called S/ S/ usually called S/ S/ general PDIF, EIAJ CP-1201, IEC60958, AES/EBU

Two-phase Input signal sampling frequency (FS) range: 28 kHz to 108 kHz

Restore system clock: 50 PS

jitter tolerance that conforms to IEC60958-3

serial audio data output format: 24-bit I2S; MSB priority, 24-bit left-to-alternate; MSB priority 16-, 24-bit right alignment

user data , Channel status data output and decoding serial audio data synchronization

decoding does not require external clock

Including actual sampling frequency calculator (required external 24.576-MHz clock clock clock )

Functional control: parallel (hardware)

function is similar to DIR1703, the pin allocation of pins is the same as DIR1703

singles Power: 3.3 V (2.7 V to 3.6 V)

Wide operating temperature: --40 ° C to 85 ° C

5 v

Packaging: 28 -pin TSSOP, pin spacing: 0,65 mm

vehicle audio external amplifier

Description

dir9001-Q1

conforms to IEC60958-3, Jeita CPR-1205 (EIAJ CP-1201 revised version), AES3, AES3, AES3, Ebutech3250 can be used to need various applications that need digital audio interfaces.

DIR9001-Q1 supports multiple output system clocks and outputData format can be flexibly applied to many application systems. Because all the functions provided by DIR9001-Q1 can be directly controlled by controlling pins, it can be easily used in the application system without microcontroller. In addition, because the channel status and user data are provided for special pipes, it can easily complete the processing of their information through connection with microcontroller, DSP, etc.

If the internal actual sampling frequency calculator is not used, the DIR9001-Q1 does not require an external clock source or resonator for decoding operation. Therefore, it is possible to reduce system costs. The operating temperature range of DIR9001-Q1 specifies that of -40 ° C to 85 ° C, so it is suitable for automotive applications.

Figure

Typical performance features

Sinusabar wave work amplifier, 0-0 kHz; crystal no load.

Power current

Resume system clock (SCKO) jitter

Device information

Acceptable two-phase input signal and two-phase input pins (RXIN)

DIR9001-Q1 can decode the two-phase signal format specified in the following standards. Generally, these standards can be called Sony/Philips Digital Interface Format (S/PDIF) or AES/EBU.

IEC60958 (formerly IEC958 revised version)

Jeita CPR-1205 123] AES3

eBU Tech3250

DIR9001-Q1 The range range and dataword length that can be decoded as follows:

The sampling frequency range is 28 kHz to 108 kHz.

maximum audio sample length is 24 bits.

Other comments on the two -phase input signal.

The capture rate of the built-in lock ring conforms to the three levels (12.5%) specified in the sampling frequency accuracy specified by IEC60958-3.

DIR9001-Q1's jitter tolerance conforms to IEC60958-3.

PLL can also be locked outside the specified sampling frequency range, but the extension range cannot be guaranteed.

Note the signal level and transmission line of the two -phase input signal.

Different signal levels and transmission lines in each standard (optical, differential, single -end).

two-phase input signal is connected to the RXIN pin of DIR9001-Q1.

Rxin pin has a 5 volt TTL level input.

optical receiver module (optical-electric converter), such as TOSLINK, is usually used for consumer applications and directly connects to the RXIN pin without adding external components.

Output waveform of the optical receiver module changes with the characteristics of each product type, so a dumping resistor or buffer amplifier may be required between the output of the light receiver module and the DIR9001-Q1 input Essence If the light receiver module is far away from the DIR9001-Q1, you need to operate carefully.

If DIR9001-Q1 is connected to the coaxial transmission line, an external amplifier is required.

If the non-optical transmission line is used, DIR9001-Q1 requires an external differential to a single-end converter, attenuator, etc. for general consumer applications.

System reset

DIR9001-Q1 reset function is controlled by the external reset pin RST.

The reset operation must be executed during the power sequence shown in FIG. 4. Specifically, DIR9001-Q1 requires 100 NS reset operations after the power supply voltage rises to 2.7V.

The state of each output pin during the reset is shown in Table 1.

Work mode and clock conversion signal output

Operating method

DIR9001-Q1 has the following three operating modes.

These modes are selected by connecting the CKSEL pin.

PLL mode: Used to discodge the two -phase input signal; always output PLL source clock

XTI mode: for clock generator; always output XTI source source Clock

Automatic mode: automatic clock source selection; output source depends on the error pin.

Operation mode Select Note:

Generally, select the PLL mode: CKSEL L decoding the two -phase input signal.

XTI mode is a mode of providing XTI source clock to the peripheral device (A/D converter, etc.); therefore, clocks and decoding data of recovery will not be output.

when the XTI source is not used, there is no need for XTI source. in this caseThe clock is not output in XTI mode.

When selecting XTI mode, the two -phase decoding function continues to work. Therefore, the results of the two -phase input state (error) and the sampling frequency calculator (the XTI source required for operation) are always monitored. In other words, the following output pins: ERROR, BFRAME, FSOUT [1: 0], CLKST, Audio, and EMPH are always enabled.

Table 2 gives the detailed information of these three modes.

(1), due to the oscillation frequency of the voltage control oscillator depends on the power supply voltage, temperature and process change, the free operating frequency of the voltage control oscillator is not a constant. frequency.

Clock conversion signal output

DIR9001-Q1 provides the output pulse that synchronizes the change in the state of lock/unlock status.

The PLL status change between the output lock and unlocking of the CLKST pin. CLKST output pulse depends only on the state change of PLL.

The clock change/conversion signal output through CLKST.

Because the signal indicates the clock conversion cycle caused by changes in the PLL state, it can be used to mute or other appropriate functions in the application.

The selection of clock source caused by the CLKSEL pin does not affect the output of CLKST.

Even in the XTI source mode CKSEL H, CLKST will change due to changes in the PLL state.

When the DIR9001-Q1 is locked in the state of the two-phase input signal, the pulse signal of the CLKST is not output. In other words, the priority of resetting is higher than CLKST.

The relationship between the lock/unlocking process, CLKST and error output, output clocks (SCKO, BCKO, LRCKO) and data (DOUT) are shown in Figure 6.

Clock Description

System clock source

DIR9001-Q1 has the following two system clock sources.

PLL source (can provide 128 FS, 256 FS, 384 FS, 512 FS, restore with built -in PLL)

XTI source (requires a 24.576-MHz resonator or external clock source.)

Two clock sources are used for the following goals.

PLL Source: Enter the signal recovery system clock from the two phases

xTI source: clock source for peripheral devices (such as A/D converter, microcontroller, etc.), which is used for the measurement clock of the measurement frequency of the internal actual sampling frequency

]

PLL clock source is an output clock built -in PLL (including VCO).

PLL clock source frequency can be selected through PSCK [1: 0] from 128 FS, 256 FS, 384 FS, 512 FS.

When the PLL is locked, the PLL clock source is the clock recovered from the two -phase input signal.

When the PLL is in a unlocking state, the PLL clock source is the built -in free run clock of VCO.

PLL clock source in the unlocking state is not constant.

(VCO free running frequency depends on the changes in power voltage, temperature, and chip wafers.)

XTI clock source description

XTI clock source is not used for it Enter the signal from the two phases to recover the clock and decoding data.

therefore, if DIR9001-Q1 is only used to recover the clock and decoding data from the two phases, the XTI clock source is not required. In this case, the XTI pin must be connected to the DGND pin.

(DIR9001-Q1 is not used to use or does not use XTI clock source pins.)

The choice method of clock source

The level of the CKSEL pin is selected from two clock sources.

The selection of the system clock source only depends on the input level of the CKSEL pin.

Enter the recovery clock and decoding data from the two phases and the decoding data requires CKSEL L settings.

Xti clock source output requires CKSEL H settings.

During the clock source conversion between the XTI source and the PLL source, the continuity of the clock cannot be guaranteed.

The automatic selection method of the clock source (clock source mode: automatic)

This method can use the DIR9001-Q1 error state to automatically select the clock source. Output the PLL source clock when Error L; the XTI source clock is output when error h.

To enable the automatic clock source selection, the CKSEL pin must be connected to the ERROR pin.

If the XTI clock source is required during the error period, it is recommended to use this method.

due to errorsThe clock source during the state is XTI. If the XTI clock source is not provided to the XTI pin, SCKO, Bcko and LRCKO will not be output during the error period.

The relationship between clock/data source and CKSEL pin and PLL state input combination is shown in Table 2.

The clock tree system is shown in Figure 7.

PLL clock source (built-in PLL and VCO) description

DIR9001-Q1 has a blocking ring (including VCO), which is used to enter from two phases input Restore the clock in the signal.

The clock from the built -in VCO output is defined as the PLL clock source.

In the locking state, the built -in ring ring generates a system clock synchronizing with the two -phase input signal.

In the unlocking state, the built -in lock ring (VCO) generates a free clock. (The frequency is not constant.)

PLL can support 128 FS, 256 FS, 384 FS or 512 FS system clock, of which FS is the sampling frequency of the two -phase input signal.

The system clock frequency of PLL is selected by PSCK [1: 0].

DIR9001-Q1 can decode the two-phase input signal through its 28 sampling frequency range (KHz to 108 KHz), which has nothing to do with the setting of PSCK [1: 0].

Therefore, DIR9001-Q1 can decoding the sampling frequency from 28 kHz to 108 kHz in all settings of PSCK [1: 0].

PSCK [1: 0] Select the relationship between the output clock (SCKO, BCKO, LRCKO) of the PLL source as shown in Table 3.

In PLL mode (CKSEL L), the output clock (SCKO, BCKO, LRCKO) is generated by the PLL source clock.

The frequency relationship of the frequency of LRCKO, BCKO, and SCKO under different sampling frequencies in the two -phase input signal is shown in Table 4.

The required PLL ring circuit filter description

DIR9001-Q1 contains a PLL, which is used to generate clocks synchronizing with the two-phase input signal.

The built -in lock ring requires an external circuit filter, which is shown below.

The operation and performance of the recommended filter components R1, C1, and C2 is guaranteed.

Instructions on circular filter components and layouts

The resistor and capacitor that constitutes a filter should be as close to DIR9001-Q1 as possible.

It is recommended to use a carbon film resistor or metal membrane resistor with a tolerance of less than 5%.

It is recommended to use a film capacitor with a tolerance of less than 5%.

If C1 and C2 use ceramic capacitors, it is recommended to use parts with low voltage coefficients and low -temperature coefficients, such as CH or C0G.

The external circuit filter must be placed on the filter pin.

GND nodes of the outer circuit filter must be connected directly with the Agnd pins of DIR9001-Q1; not to combine with other signals.

The outer ring filter configuration and the connection to DIR9001-Q1 are shown in Figure 8.

The recommendation of the circular filter component is found to Table 5.

XTI clock source and oscillating amplifier description

This clock is driven by a built -in oscillating amplifier or entered the XTI tube foot from the external clock, which is defined as the XTI source. The XTI source uses 24.576 MMB base frequency resonator or external 24.576 MMC clock.

DIR9001-Q1 Requires XTI source for the following purposes:

actual sampling frequency calculator measurement benchmark clock

XTI source mode Clock source (CKSEL H settings)

(that is, if DIR9001-Q1 only decodes the two-phase input signal, it does not require XTI.)

XTI clock source is as follows as the following One of the two methods is provided; the details are shown in Figure 9.

By connecting the resonant to the built -in amplifier, set the oscillation circuit

Connect the resonator to the built -in amplifier to set up an oscillating circuit:

connect a 24.576 MM resonator between the XTI pin and the XTO pin.

resonant should be the basic mode type.

Crystal resonant or ceramic resonator can be used.

load capacitors CL1, CL2, and current limit resistor RD depending on the characteristics of the resonant.

XTI pins and XTO pins do not require external feedback resistors, because the device contains appropriate resistors.

XTO pins are not allowed to have loads except resonator.

To connect the external oscillator circuit or oscillator module:

Provide 24.576 MMC clocks on the XTI pin

Please note that the XTI pin does not allow 5 volt voltage; it is a simple CMOS input.

XTO sales must be opened.

The oscillating amplifier operation description:

The built -in oscillating amplifier always works.

If the XTI source clock is not used, the XTI pin must be connected to DGND.

In order to reduce power consumption, it is recommended not to use the XTI source clock.

In XTI mode (CKSEL H), the output clock (SCKO, Bcko, LRCKO) is generated by the XTI source clock.

The relationship between output clock frequency (SCKO, BCKO, LRCKO) and XSCK pin settings in XTI source mode is shown in Table 6.

Data description

Decoding serial audio data output and interface format

DIR9001-Q1 supports the following 4 decoding data formats.

16 bits, MSB priority, right alignment

24 bits, MSB priority, right alignment

24 bits, MSB, MSB, MSB, MSB, MSB, MSB, MSB, MSB Priority, left alignment

24 bits, MSB priority, I2S

The decoding data in all formats are MSB priority and 2S supplementary code.

The decoding data is provided by DOUT.

The format of the decoding data is selected by FMT [1: 0].

The data format set by each fmt [1: 0] pins is shown in Table 7.

FIG. 11 shows the relationship between BCKO, LRCKO and DOUT in each format.

Channel status data and user data serial output

DIR9001-Q1 can input signal output and from the two phases in and out. Audio data synchronous channel status data and user data.

Each output data has its own special output pins.

Channel status data (C, hereinafter referred to as the following) via the Cout pin.

User data (U, here an abbreviation U) is output through the UOUT pin.

C and U output and input signals from the two phasesRestore LRCKO synchronization.

The LRCKO polarity recovered from the two phases depends on the FMT [1: 0] settings.

In order to detect the channel status data or the top of the user data block, the BFRAME tube foot is provided.

If the front guide code B is detected in the received two-phase signal, the BFRAME PIN outputs the high level of the 8-LRCK cycle.

When processing these data with a microcontroller or register circuit, LRCKO is used as a data input clock, and the output pulse on the BFRAME pin is used as a top signal.

FIG. 13 shows the relationship between LRCKO, BFRAME, DOUT, COUT and UOUT.

When in the XTI mode and PLL locking state, Cout and UOUT output L.

Channel status data output terminal

Design Institute R9001-Q1 can output part of the channel status information of some channel status information (bit 1 1 1 of audio and EMPH special pins (bit 1 Position 3).

The channel status information that can be output from the special pipe foot is limited to the information from the L channel.

If the channel status information other than the audio or EMPH is required, or the information of the R channel, you can use the channel status data on the COUT pin synchronization with the two -phase input signal.

These outputs are synchronized with block tops.

The information output by the special pipe foot can be shown below.

Audio pin

This is the output pins of the audio sample information of the channel status data bit 1.

electromagnetic pulse needle

This is the output tube of the emphasis information of channel status data level 3.

Error and error treatment

Error output instruction PLL unlocks the data of the loss of two -phase encoding rules (two -phase error and frame length error).

For data that cannot be detected by the front guide code B, M, W, PLL responds to unlocking.

Error treatment function and error output pin

DIR9001-Q1 have data error detection function and error output pin Error.

Error pins are defined as logic or detection of data errors and coupling error detection.

error rising edge is synchronized with CLKST.

error drop edge andLrck synchronization.

The relationship between the data error and the detection of the test errors is shown in Figure 15.

The status and details of the error pins are shown in Table 10.

Error processing error processing and error detection and error processing of error detection and error processing of the unlisted verification

for PCM data, for PCM data, for PCM data, Implement internal insertion processing of previous data.

For non -PCM data, do not execute internal insertions, directly output data without processing. (Non -PCM complaints are the status of the ape.

Other errors

The changing error of the sampling frequency: The rapid continuous change or non -continuous change of the input sampling frequency causes the lock loop to be lost.

Calculation of actual sampling frequency

DIR9001-Q1 Calculate the actual sampling frequency of the two phases input signals, and output the result through a dedicated pin.

To use this function, we must provide the 24.576 MHz clock source to the XTI pin. The 24.576-MHz clock is used to measure the reference clock to calculate the actual sampling frequency.

If the XTI pin is connected to DGND, the calculation of the actual sampling frequency is not performed.

If there is an error in the XTI clock frequency, the calculation results and range will be shifted accordingly.

This output is the result of calculating the sampling frequency. It is not the sampling frequency information of the channel status data (bit 24– bit 27).

The sampling frequency information of the channel status data (bit 24-127) does not output through these pin.

The calculation result was decoded into 2 digits of data and output it on the foot [1: 0] tube.

If the locking loop is locked but the sampling frequency exceeds the range, or if the locking loop is unlocked, the output FSOUT [1: 0] HL to indicate the abnormality.

When the XTI source clock was not provided before power -on, fsout [1: 0] always output LL.

When the XTI source clock stops, the FS calculator saves the last value of the results of the FS calculator.

If the XTI source clock is provided, the FS calculator will resume operation.

The calculation value will be kept until reset.

Fsout [1: 0] The relationship between output and sampling frequency range is shown in Table 11.

Typical circuit connection

FIG. 17 shows a typical circuit connection.

Note: R1: Circuit filter resistance, 680 u0026#8486; R2: current limit resistance; generally use 100 u0026#8486; –500 u0026#8486;Crystal resonator.

C1: Circle filter capacitor, 0.068 μF.

C2: Circle filter capacitor, 0.0047μF.

C3, C4: OSC load capacitor; usually 10 PF -30 PF capacitors, but this depends on crystal resonant and PCB layout.

C5, C8: 10-μF electrolytic capacitor depends on the quality and PCB layout.

C6, C7: 0.1-μF ceramic capacitor depends on the power quality and PCB layout.

X1: Crystal resonator, when the XTI clock source is required, use a basic resonator of 24.576 MMS.