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2022-09-16 16:00:09
BUF08832 is a programmable gamma voltage generator and high conversion rate VCOM integrated double -row memory
Features
10-bit resolution
8 channel P-gamma rays
single channel P-vcom
High conversion rate vCOM: 45V/μs
16 times rewriting non -easy -to -sex memory
two Independent pins can be selected for the repository
orbid to the rail transfers
-300 millival minimum orbit (10mA)
- gt; 300ma maximum maximum Output
Low power current
Power supply voltage: 9V to 20V
Digital power supply: 2V to 5.5V
dual-line interface: support 400kHz and 3.4MHz
Application
TFT-LCD reference driver
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Explanation
buf08832
Provides eight programmable gamma channels and a programmable VCOM channel.The final GAMMA and VCOM values can be stored in non -easy -to -loss memory on the chip. In order to allow programming errors or liquid crystal monitors (LCD) panels, BUF08832 supports up to 16 writing operations on the storage memory.
BUF08832 has two independent repository, allowing two different gamma curves to be stored at the same time to switch between gama curves.
All Gamma and VCOM channels provide rail transfers, usually swinging to 150mv under the 10mA load. All channels use dual -line interface programming, supporting standard operations up to 400kHz and high -speed data transmission up to 3.4MHz.
BUF08832 is the patent of instruments made of Texas, the most advanced, high -pressure CMOS process. This process provides very dense logic and power supply voltage operations up to 20V. BUF08832 is a #8482; packaging provided in the HTSSOP-20 power board, and the specified temperature is -40 ° C to+85 ° C.
Related products 
TA +25 ° C, vs +18V, vsd +2V, RL 1.5K ground, CL 200pf, unless there is another instructions.
Application information
General Rules
buf08832 programmable benchmark voltage allows eight programming gamma reference outputs and a VCOM output, each each, each VCOM output, each time The output has 10 -bit resolution. BUF08832 via high -speed dual -line programming interface. The final gamma and VCOM values can be stored in non -loss -loss memory. In order to allow programming errors or liquid crystal monitors (LCD) panels, BUF08832 supports up to 16 times to write operations on board memory. BUF08832 has two independent repository, allowing two different gamma curves to be stored at the same time to facilitate dynamic switch between gamma curves.
BUF08832 can use 9V to 20V analog power supply voltage and 2V to 5.5V digital power supply. To use digital power to avoid excessive current and power consumption, or if you only connect to the simulation power supply for a long time, it may even damage the device. For typical configurations of BUF08832, see Figure 13 and Figure 14.
Overview of the dual -line bus
BUF08832 communicates through the dual -line interface of industrial standards to receive data from the mode. This model uses a two -line open drain interface to support multiple devices on a bus. The bus is only driven to low logic. The equipment that initiates communication is called the main device, and the device controlled by the main device is from the device. The host generates serial clock on the clock signal line (SCL), controls the bus access, and generates start and stop conditions.
In order to address specific devices, when the SCL is at high electricity, the host starts the startup condition by pulling the data signal line (SDA) from high logic levels to low -logo levels.
All the slave on the bus was shifted from the machine address byte byte by the SCL rising edge. The last instruction was to perform reading operations or writing operations. During the ninth clock pulse period, the address of the addressing was responded to the host by generating a response and lowering the SDA.
Then start the data transmission, send 8 -bit data, and then send a confirmation bit. During the data transmission process, when the SCL is high, the SDA must be stable. When SCL is high, any change of SDA is explained as startup or stop conditions.
Once all the data is transmitted, the host will generate a stop condition. When the SCL is high, the SDA will be pulled from low to high. BUF08832 can only be used as a device; therefore, it never drives SCL. SCL is only the input of BUF08832. 
The address of the buf08832 is 111010x, where X is the state of the A0 pin. When the A0 pin is low, the device is confirmed at the address 74h (1110100). If the A0 pin is high level, the device is inThe address is confirmed on 75h (1110101). Table 1 shows A0 pin settings and BUF08832 address options.
Other valid addresses can be implemented by simple mask changes. Please contact your TI representative to obtain information.
(1), the panel selection value that must be used.
(2) When the driver is driven by large capacitance load, the appropriate phase margin must be selected.
(3), GNDA and GNDD must be connected together.
(4), needle 7 and 19 are compared with the pinnacle 19, and a set of capacitors displayed on the pin 19 shass the two needle feet.
(5), the output pin is not recommended to use the RC combination; please refer to the output protection part.
(1), GNDA and GNDD must be connected together.
(2), needle 7 and 19 are opposed to the pinnacle 19, and a set of capacitors displayed on the pin 19 shass the two needle feet.
(3), the output pin is not recommended to use the RC combination; please refer to the output protection part.
Data rate
The dual -line bus runs with one of the three speed modes:
standard: allow clock frequency to reach 100kHz;
Quick: The clock frequency is as high as 400kHz; and
high -speed mode (also known as HS mode): The clock frequency is as high as 3.4MHz.
BUF08832 is completely compatible with all three modes. Under standards or fast mode, the use of equipment does not require special operations, but the high -speed mode must be activated. To activate the high -speed mode, send a special address byte 00001 XXX after starting the condition, SCL ≤ 400kHz; where XXX is the only bit of the host of HS, it can be any value. This byte is called HS main code. Table 2 provides a reference for the high -speed mode command code. (Please note that this configuration is different from the normal address bytes, and the low position does not indicate the read/write status.) No matter the value of the last three digits, the BUF08832 will respond to the high -speed command. BUF08832 is not recognized this byte; the communication protocol is prohibited to confirm the HS main code. After receiving the main code, BUF08832 opens its HS mode filter and communicates at a frequency of up to 3.4MHz. By generating uninterrupted repetitions, you can start additional high -speed transmission without sending HS mode bytes. BUF08832 exits the HS mode under the next stop condition.
General call reset and power power
buf08832 response general call resetByte 00h (0000 0000 0000), followed by data byte 06H (0000 0110). BUF08832 confirms these two bytes. Table 2 provides a reference code for the general call reset command. After receiving the general call reset, the BUF08832 will perform a complete internal resetting, as if it has been turned off and then opened. It always confirms the general call address bytes of 00H (0000 0000), but it is not confirmed that any general call data bytes other than 06H (0000 0110) are not confirmed. 
Output voltage
The output value of the buffer is determined by the decimal value of an analog power supply voltage (VS) and the decimal value of the binary input code used to program the buffer. Use Formula 1 Calculate this value:
BUF08832 output can usually achieve full voltage output changes within 5 μs; no intermediate steps are required.
Update the DAC output voltage
Because the BUF08832 has a dual cushioning register structure, the update digital converter (DAC) and/or VCOM registers are different from the update DAC and/or VCOM output voltage. There are two ways to update the DAC/VCOM output voltage.
Method 1: When you need to change the DAC/VCOM output voltage immediately after writing the DAC register, use method 1. For each transaction, the host sets the data bit 15 to ""1"". The DAC/VCOM output voltage update occurs after receiving the 16th data bit that receives the currently written register.
Method 2: When all DAC/VCOM output voltage needs to be changed at the same time, use method 2. First, the host uses data bit 15A ""0"" to write the required DAC/VCOM channel. Then, when the last DAC/VCOM channel is written, the main device sets the data bit 15 to ""1"". All DAC/VCOM channels are updated at the same time after receiving the 16th data bit.
Non -easy loss memory
BKSEL pin
BUF08832 has 16x redevelopment capabilities of non -easy loss memory. In addition, BUF08832 can store two different gamma curves in two different non -prone memory libraries. Each non -easy -to -sex memory has 16 times the rewriting ability. Use the external input pin BKSEL to select one of the two available cylinder groups. When PIN is low, choose Bank0; when Pin is HIGH, select Bank1.
When the BKSEL pin changes the state, the BUF08832 is to obtain the DAC/VCOM value of the final programming from the non -volatile memory associated with this newly selected group. When power -on, the state of the BKSEL pin determines which memory group is selected.
The I2C host can also use the software to update (acquisition) DAC register control with the final programming non -easy -to -loss memory value. The acquisition bank depends on the state of BKSEL.
General acquisition command
The general acquisition command is used to update everything. The general -purpose acquisition command is used to update all programming values stored in non -easy -to -sex memory. The single channel collection command only updates the DAC/VCOM register and DAC/VCOM output corresponding to the DAC/VCOM address used in the single channel collection command.
The following is the sequence steps for starting conventional channel collection:
1. Make sure that the BKSEL is in the required state and stabilize at least 1ms.
2. Send the start -up condition on the bus.
3. Send an appropriate device address (based on A0), read/write position low. BUF08832 confirms this byte.
4. Send a DAC/VCOM pointer address byte. Setting bit d7 1 and d6 0. VCOM-D0-5 bits are effective. Although BUF08832 confirms 000000 to 010111, it only stores and returns data from the following addresses:
000000 to 000111- 010010
For Reading from 010011 to 010111, it returns 0000. The effective DAC/VCOM address is shown in Table 4.
5. Send parking conditions on a bus.
After the command is issued, about 750 μs (± 80 μs) is issued. All DAC/VCOM registers and DAC/VCOM output voltage will change to the corresponding, appropriate non -easy -to -miss memory value.
Single channel collection command
The following is the step of starting single channel collection:
1. Make sure that the BKSEL is in the required state and stabilize at least 1ms.
2. Send the start -up condition on the bus.
3. Send the device address (based on A0), read/write bit low. BUF08832 confirms this byte.
4. Use the DAC/VCOM address corresponding to the output to send the DAC/VCOM pointer address byte and update the register with OTP internal deposits. Setting bit d7 0 and d6 1. Bit D5-D0 is a DAC/VCOM address. Although BUF08832 confirms 000000 to 010111, But it only stores and returns data from the following addresses:
- 000000 to 000111- 010010
It returns from 001000 to 010001, and from 010011 to 010111 0000 read. The effective DAC/VCOM address is shown in Table 4.
5. Send parking conditions on a bus.
After the command was issued, about 36 μs (± 4 μs) was issued, and the specified DAC/VCOM register and DAC/VCOM output voltage changed to a proper memory value.
Maxbank
BUF08832 can provide users with a specific DAC/VCOM channel non -easy -to -loss memory of non -easy memory memory. This information is provided by the register at the pointer address 11111.
There are two ways to update Maxbank registers:
1. After starting a collection command, BUF08832 updates the Maxbank register with a code, which corresponds to this specific channel memory that has Number of times.
2. After the general account command, BUF08832 uses the maximum number of codes to update Maxbank registers corresponding to the most commonly used channel (OUT1-8 and VCOM).
Maxbank is a reader that can only be updated by executing conventional or single -channel collection.
Table 3 shows the relationship between the number of programming times of non -loss -loss memory and the corresponding state of the Maxbank register.
Qiqi verification error correction school correction
buf08832 provides a single -bit -puppet verification error correction for the data stored in non -easy -to -see storage to improve non -non -non -errors The reliability of easy loss memory. If the unit's non -easy -to -lose sex memory fails, the BUF08832 will correct it and update the corresponding DAC with the expected value when obtaining its memory.
If multiple non -susceptible memory of a channel fails, BUF08832 will not be able to correct it and use the default value 1000000000 to update the corresponding DAC/VCOM.
DIE_ID and DIE_REV registers
Users can read from the address 111101 to verify whether the buf08832 exists in the system. When the address is read, BUF08832 returns 001000101000000.
The user can also determine the mold version of the buf08832 by reading from the register 111100. When Reva mold is storedAt that time, BUF08832 returned 00000000000000. Revb will be specified as 000000000001, which is pushed according to this.
Reading/writing operation
You can perform reading and writing operations on a single DAC/VCOM or multiple DAC/VCOM. Write into DAC/VCOM registers and write non -easy -to -miss memory. D15 – D14 of the highest effective bytes of data is determined whether the data is written into DAC/VCOM registers or non -loss memory.
Reading/writing: DAC/VCOM register (easy to lose memory)
BUF08832 can be read from a single DAC/VCOM or multiple DAC/VCOM in a single communication transaction, or write it into, or write into it A single DAC/VCOM or multiple DAC/VCOM registers. The DAC pointer address starts with 000000 (corresponding to OUT1) to 000111 (corresponding to OUT8). The VCOM address is 010010.
Perform the writing command by setting the reading/writing position as a low position. Set the reading/writing position to the high -level execution of reading transactions.
Writing: DAC/VCOM register (easy to lose memory)
Write a single DAC/VCOM register:
1. Send the startup condition on the bus.
2. Send the device address, read/write position low. BUF08832 confirms this byte.
3. Send a DAC/VCOM pointer address byte. Setting bit d7 0 and d6 0. Bit D5 -D0 is a DAC/VCOM address. Although BUF08832 confirms 000000 to 010111, it only stores and returns data from the following addresses:
000000 to 000111
- 010010
For Reading from 010011 to 010111, it returns 0000. The effective DAC/VCOM address is shown in Table 4.
4. Register to send two bytes of data to specify. Start sending the highest effective bytes (bit D15 – D8, of which only bits D9 and D8, and bit D15 – D14 must not be 01), and then send the lowest effective byte (bit D7 – D0). The register was updated after receiving the second byte.
5. Send stop or start conditions on the bus.
BUF08832 confirms each data byte. If the host stops communication by sending stop or starting conditions on the bus, the specified register will not be updated. Update the DAC/VCOM register is different from updating the DAC/VCOM output voltage; please refer to the update DAC output voltage section.
The process of updating multiple DAC/VCOM registers is the same as when updating a single register. However, it is not to send stop conditions after writing the addressing register, but continue to send data to the next register. When sending additional data, the BUF08832 will automatically execute the follow -up register in order. The process will continue until all the required registers have been updated or sent to stop or start.
Write multiple DAC/VCOM registers:
1. Send the start -up condition on the bus.
2. Send the device address, read/write position low. BUF08832 confirms this byte.
3. Send an OUT1 pointer address byte to start with the first DAC, or send the pointer address byte, no matter which DAC/VCOM is the first DAC/VCOM sequence to be updated. BUF08832 starts with the DAC/VCOM and gradually executes the follow -up DAC/VCOM in order.
4. Send the data byte; first send the highest effective byte (bit D15 – D8, only D9 and D8 are meaningful, and the bit D15 – D14 cannot be 01), and then the minimum effective byte byte (D7 – D0). The first two bytes are used for DAC/VCOM, which are located in the previous step. After receiving the second byte, the DAC/VCOM register is automatically updated. The next two bytes are used for the following DAC/VCOM. The DAC/VCOM register is updated by the byte after receiving the fourth register. This process will continue until all the registers of all DAC/VCOM have been updated. BUF08832 continues to accept a total of 18 DAC data; however, the two data sets after the 16th data set are meaningless. The 19th set of data is suitable for VCOM. Group 20 data is meaningless. This method cannot be used to access the writing disabled. It must be written with a single DAC register process.
5. Send stop or start conditions on the bus.
BUF08832 confirm each byte. To terminate communication, please send stop or start on the bus. Only DAC registers that receive two bytes of data are updated.
Reading: DAC/VCOM/Other registers (easy loss memory)
Reading the register returns the data that is stored in the DAC/VCOM/other registers.
Read a single DAC/VCOM/other registers:
1. Send the start -up condition on the bus.
2. Send the device address, read/write position low. BUF08832 confirms this byte.
3. Send DAC/VCOM/other pointer address byte byte. Setting bit d7 0 and d6 0;Bit D5 -D0 is DAC/VCOM/other addresses. Note: BUF08832 only stores and returns data from the following address:
- 000000 to 000111
- 010010
- 111100 to 111111
For from 001000 To 010001, and reading from 010011 to 010111, it returns 0000. The effective DAC/VCOM/other addresses are shown in Table 4.
4. Send start or stop/start conditions.
5. Send the correct device address, read/write position high. BUF08832 confirms this byte.
6. Receive data of two bytes. They are targeted at specified registers. First receive the highest effective byte (bit D15 – D8); secondly, the lowest effective byte (bit D7 – D0). In the case of the DAC/VCOM channel, it is meaningless to digit D15-D10.
7. After receiving the first byte, confirm.
8. Send stop or start conditions or confirm the second byte to end reading transactions on the bus.
You can terminate communication by sending premature stop or starting conditions on the bus, or uncertainty.
Read multiple registers:
1. Send the start -up condition on the bus.
2. Send the device address, read/write position low. BUF08832 confirms this byte.
3. Send an OUT1 pointer address byte to start with the first DAC, or send the pointer address byte, no matter which register is the first register in the DAC/VCOM sequence to read. BUF08832 starts with the DAC/VCOM and gradually executes the follow -up DAC/VCOM in order.
4. Send start or stop/boot condition on the bus.
5. Send the correct device address, read/write position high. BUF08832 confirms this byte.
6. Receive data of two bytes. They are used to specify the DAC/VCOM. The first byte to receive is the highest effective byte (bit D15-D8; only D9 and D8 are meaningful), and the next one is the lowest effective byte (bit D7-D0).
7. After receiving the data of each byte, confirm.
8. When all the required DACs are read, send a stop or startup condition on the bus.
The communication can be terminated by sending premature stop or starting conditions or not sending confirmation bits on the bus. In this operation mode, it does not support reading register Dieid, Dierev, and Maxbank (must read these values with a single register read method)Essence
Writing: Non -easy -to -miss memory of the DAC register
BUF08832 can write a single DAC/VCOM non -volatile memory in a single communication transaction. Unlike BUF20820, it does not support writing multiple non -prone memory memory in a single transaction. The effective DAC/V COM pointer address starts with 000000 (corresponding to OUT1) to 000111 (corresponding to OUT8). The VCOM address is 010010.
When programming the non -easy -to -see memory memory, the simulated power supply voltage must be between 9V and 20V. Perform the writing command by setting the reading/writing position as a low position.
Write a single non -prone loss register:
1. Send the startup condition on the bus.
2. Send the device address, read/write position low. BUF08832 admits this byte. Although BUF08832 confirms 000000 to 010111, it only stores and returns data from the following addresses:
000000 to 000111- 010010
For from 001000 to 010001, and from from from 001000 to 010001 Reading from 010011 to 01011, it returns 0000. See Table 4 at the DAC/VCOM address.
3. Send a DAC/VCOM pointer address byte. Setting bit d7 0 and d6 0. Bit D5 -D0 is a DAC/VCOM address.
4. Send two bytes of data for the non -volatile register of the specified DAC/VCOM. First send the highest effective bytes (bit D15 – D8, of which only D9 and D8 are data bits, and bit D15 – D14 must be 01), and then the lowest effective byte (bit D7 – D0). The register was updated after receiving the second byte.
5. Send parking conditions on a bus.
BUF08832 confirms each data byte. If the host is terminated in advance by sending stop or starting conditions on the bus, the specified non -volatile register is not updated. Writing non -easy -to -see registers will also update the DAC/VCOM register and output voltage.
DAC/VCOM registers and DAC/VCOM output voltage are updated immediately, rather than the programming of non -loss memory required 250 μs. Once a non -easy -of -sex register is issued to write a command, at least 250 μs shall not communicate with the BUF08832. While non -easy -to -miss memory, the writing or reading data through serial interface is being written to endanger the integrity of the stored data.
Reading: non -easy -to -sex memory of the DAC register
Read data in the non -volatile register of a specific DAC/VCOM channelThe host must first issue a universal collection command, or select the appropriate DAC/VCOM channel to send a single collection command. This operation updates the DAC/VCOM register and DAC/VCOM output voltage at the same time. The host can then read from the appropriate DAC/VCOM register as mentioned earlier.
The programmable VCOM limit
BUF08832 VCOM output has a programmable upper limit and lower limit. These restrictions are the same as the interface as the DAC register. These registers are written and read through the two line bus. The limiter address of the upper limit and lower limit is 1E and 1F, respectively. See Table 4 for the register pointer address.
When power -on or general call reset, the DAC register (channel 1 to 8 and VCOM) is set to 200 (default values), corresponding to the medium -scale output of 10 digits of DAC. The upper and lower limit registers are set to 3FF and 000, respectively. Therefore, if there is no programming, these restrictions are transparent.
BUF08832 uses dual cushioning registers. Data input is stored on the first layer. According to the application, the input can be locked to the DAC output. DAC is updated only when the second layer is enabled.
The upper limit and lower limit can be programmed as any required value to limit VCOM output. This restrictions can be programmed before or after programming. Because the data input is stored in the first layer of locks, the VCOM output is limited according to the following rules:
1. If the VCOM OTP is written into it, the VCOM input is always stored in OTPs in OTP Essence The limit comparison occurs only before the DAC output.
2. If the VCOM input is higher than the upper limit, the upper limit is locked to the DAC output. Read the upper limit of the reading DAC register.
3. If the VCOM input is lower than the lower limit, the lower limit is locked to the DAC output. Read the lower limit of the Reading DAC register.
4. If the VCOM input is between the upper limit and the lower limit, the programming value is locked to the DAC output. Read the DAC register and return the programming value.
5. If the upper limit is lower than the lower limit, the BUF08832 will ignore these limits and lock the programming value to the DAC output. Read the DAC register and return the programming value.
There are two OTP groups and each of the two restricted registers. The OTP operations on these two addresses are effective, just like the OTP of the DAC register. 
The GAMMA control selected by the end user
Since there are two sets of non -loss -loss memory in BUF08832 It is suitable for providing two levels of Gamma control using BKSEL pins, as shown in Figure 21. When the state of the BKSEL pin changes, BUF08832 updates all 9 programmable buffer outputs at the same time after 750 μs (± 80 μs).
To update all 9 programmable output voltages by hardware, please switch the BKSEL pin to switch between the Gamma curve 0 (stored in Bank0) and Gamma curve 1 (stored in Bank1).
After about 750 μs, all DAC/VCOM registers and output voltage were updated at the same time.
Dynamic gamma control
Dynamic gamma control is a technology used to improve the quality of LCD TV image. This technology usually needs to switch the Gamma curve between the frames. It takes 750 μs to transmit data from non -loss -loss memory to DAC registers, so switching between two GAMMA curves with BKSEL pins usually does not provide good results. However, dynamic GAMMA control can still be achieved by storing two GAMMA curves in the external EEPROM and directly writing a DAC register (Volatile).
The dual register input structure saves programming time by allowing the updated DAC value to pre -stored to the first register group. When the picture is still displayed, this data can be stored. Because the data is only stored in the first register group, the output value of the DAC/VCOM remains unchanged and shows that it is not affected. At the beginning or end of the photo frame, you can quickly update the DAC/VCOM output by writing ""1"" at the 15th place of any DAC/VCOM register (therefore, gamma voltage). For more information on the dual register input structure operation, please refer to the update DAC output voltage section.
To update all 9 programmable output voltages at the same time through the software, please perform the following operations:
Step 1: Write to the register 1-1, bit 15 is always ""0"".
Step 2: Write any DAC/VCOM registers with the same data. Make sure the bit 15 is set to ""1"".
All DAC/VCOM channels were updated at the same time after receiving the last data.
Output protection
BUF08832 output level can safely produce and absorb the current level shown in Figure 1 and 2. However, in other modes, preventive measures must be taken to prevent the output level from being damaged by excessive current. Output (out1 to OUT8 and VCOM) includes ESD protection diode, as shown in Figure 22. Under normal circumstances, these diodes do not drive, and they are passive during typical device operations. Unusual working conditions may occur where the diode is likely to conduct electricity, which may cause it at a high or even destructive current level. When the voltage on the output exceeds (vs)+0.5V, or drops to GND – 0.5V, the most likelyThese situations are now.
When the output pins are connected to a large capacitor and a BUF08832 power supply, this source (VS) will occur suddenly. Remove the power supply can turn the capacitor to discharge the diode through the current. The energy released during high current flow can cause the power consumption of the diode to exceed the limit. High current protection is shown in Figure 13, which can be provided by connecting the current -limited resistor with the output. Select a resistance value and limit the current level to the maximum rated value of a specific pin.
General Power Plate Design
Considering matters
BUF08832 uses armal enhanced PowerPad packaging. This packaging is constructed with a lower -loaded lead frame, and the mold is installed on it; see Figure 23 (a) and Figure 23 (b). This layout causes the lead frame to be exposed to a hot pad at the bottom of the packaging; see Figure 23 (C). The thermal pads directly contact the mold; therefore, it can obtain excellent thermal performance by providing a good heat path away from the hot