Features

● Single power supply+3.3V power supply

● B/LVDS receiver input to receive LVPECL signal [123

]

● three state output

● Signal loss (LOS) pin detection non -driving bus

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receiver Enter threshold lt; ± 100 mv

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1.4NS's rapid transmission delay (typical value)

● low jitter 400 Mbps full differential data Path

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Compatible with BLVDS 10-bit Serdes (40MHz)

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Compatible with ANSI/TIA/EIA-644-A LVDS standard

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Provide SOIC and space -saving LLP packaging

● Industrial temperature range

] DS92001

B/LVDS-BLVDS buffer receives the BLVDS input signal and provides BLVDS output signals. In many large systems, the signal is distributed on the back panel. One of the limitation factors of the system speed is the distance between the existence root length or the non -standard receiver on the transmission line and the non -standard receiver on the single card. Although it is generally believed that in order to maximize the system performance, this distance should be as short as possible, but the packaging connector in the real world is usually difficult to make the storage roots as short as possible.

DS92001's edge conversion is optimized for multi -point backplates with switching frequency of 200 MHz or below. In some systems that may exist, the output edge rate is very critical. Using slow conversion can obtain a longer -stained root length.

The DS92001 provided in the packaging of LLP (Portless Drotting Framework) will allow the receiver to enter a very close to the main transmission line to improve the system performance.

The wide input dynamic range allows DS92001 to receive differential signal message sources from LVPECL and LVDS. This will allow the device to act as the role of the LVPECL BLVDS converter at the same time.

LOS pin detects non -drive B/LVDS bus status at the input terminal and provides effective low output. When the input is not driven, the LOS pin can be connected to the pins (EN) of the device's output to produce a three -state output state. LOS pin can also be used to inform the system bus status locally.

Connection and Fragments

Function operation

Order information

DC test circuit [123 ]

AC test circuit and time -order diagram

[ 123]

Typical application

Application information

DS92001 can be used as a stubborn hidden device . In many systems, the signal is distributed on the back panel. One of the restrictions of the system speed is the distance between the existence root length or the non -restricted receiver on the transmission line and the unlimited receiver on a single card. See Figure 10. Although it is generally believed that in order to maximize the system performance, this distance should be as short as possible, but the packaging problems in the real world and PCB design often make it difficult for the stubes to be as short as the designer's hope. DS92001 is provided in the packaging of LLP (lead -free lead framework) packaging. It allows the receiver to place the receiver on the backplate that is very close to the main transmission line, or close to the connector on the card, thereby improving the system performance. The long record of the LVDS receiver can be placed after DS92001. This very small LLP packaging saves 75%of space than SOIC packaging.

DS92001 can also be used as relay, as shown in Figure 11. The signal is restored and re -drive the next paragraph with the maximum intensity. DS92001 can also be used as a level converter because it accepts LVDS, BLVDS and LVPECL input.

Visual distance detection

LOS pin running in the normal operation of the device (| 100 | mv ≤VID ≤ | 2 | v) presents a logic high level. When normal transmission stops, the Los pin is asserted low. When the signal source is removed or closed (three states). When the input signal voltage (VID) is less than | 10 | millions, the LOS pin is asserted low. For normal operations, the rising and decrease time provided to B/LVDS input must be faster than 20 -nan seconds (20%to 80%) to avoid loss of signal detection. Typical input jump is within the range of 1-3 nano. In the case of signal attenuation (such as valid signal to three -state signals), the slope should be monotonous to avoid small failures in line detection.

Visual distance detection-low output

Power supply decoupled consultation

Winging capacitors must be used on the power pins. Using high -frequency ceramics (recommended on the surface with surface stickers) at the power pins of 0.1 μF and 0.01 μF capacitors, the minimum capacitor is closest to the device power supply foot. The additional decentralized capacitors on the printing circuit board will improve the decoupling. You should use multiple holes to be coupledThe capacitor is connected to the power plane. 10 μF (35V) or a larger solid pillar container should be connected to the power supply entrance point on the printed circuit board between the power supply and ground.

PC board precautions

Use at least 4 PCB plates (from top to bottom): LVDS signals, grounding, power supply, TTL signals.

isolate the TTL signal from the LVDS signal, otherwise the TTL signal may be coupled to the LVDS line. It is best to put the TTL and LVDS signals on different layers, and these layers are isolated from the power/horizon.

Make the drive and receiver as close to the (LVDS port side) connector as much as possible.

For the PC board packaging of LLP, please refer to the application description of AN-1187 Lead-free lead framework packaging . It should be noted that the optimization signal integrity (minimize the jitter and noise coupling), the LLP hot floor pad is a metal (usually a copper) rectangular area, which is located below the packaging. As shown in Figure 12, it should be connected to the ground. And match the size of the exposed pads on the PCB (1: 1 ratio).

Micro -division record

Use the controlled impedance trajectory of different impedance matching of the transmission medium (ie cable) and terminal resistance. Once the difference is left to the IC, they should be as close as possible (the length of the short -term should be less than 10 mm). This will help eliminate reflexes and ensure that noise coupling is a common phenomenon-pattern. In fact, we have seen that the noise of the 1mm differential signal is much smaller than that of the 3mm trace line radiation, because the closer the traces of the magnetic field, the better. In addition, the noise generated on the differential line is more likely to be manifested as the co -mode emitted by the receiver.

The electrical length between the matching lines is reduced to reduce the crooked. The phase difference between the crooked pair of signals means that the phase difference between the signals will destroy the magnetic field of the differential signal offset the advantage, thereby generating electromagnetic interference. For different trajectories, don't just rely on automatic wiring function. Check the size to match different impedances and provide an isolation line for differential movements. To minimize online holes and other discontinuous quantities.

Avoid 90 #730; circles (this will lead to impedance discontinuity). Use arc or 45 #730; slope.

In a pair of records, the distance between the two records should be minimized to maintain the co -mode suppression of the receiver. On the printing circuit board, the distance should be kept constant to avoid the discontinuousness of differential impedance. Mild violations are allowed at the connection point.

Termination

Use terminal resistance that matches the most impedance or transmission line. For point -to -point links, the resistance should be between 90 #8486; and 130 #8486; Multi -point (middle drive) or multi -point configuration is usually terminated at both ends. Due to the load effect, the end value may be less than 100 #8486; andAnd within the range of 50 #8486; to 100 #8486;. Remember, the current output requires the terminal resistance to generate differential voltage.

1%-2%resistance on the surface is the best. The distance between PCB storage, component lead, and the distance from the terminal to the receiver should be minimized. The distance between the terminal and the receiver should be less than 10 mm (maximum 12 mm).

Detecting LVDS transmission line

Always use high impedance ( gt; 100k #8486;), low -capacitor ( lt; 2PF) oscilloscope probe, wide range (1GHz). Inappropriate detection will produce the result of deception.

Fault protection function

BLVDS receiver is a high -gain, high -speed device, which enlarge a small differential signal (30mV) to the BLVDS output drive level. Due to the high gain and strict threshold of the receiver, you should pay attention to prevent noise from appearing as a valid signal.

The internal fault safety circuit design of the receiver is used to provide/absorb a small amount of current, providing fault protection for the input of floating, end -connecting or short -circuit receivers (high -level output voltage).

1. Termination input. If the driver is broken (the cable is pulled out), or the drive is in a power -off state, the BLVDS output will be in a high state again, even if the end of the cable 100 is the same #8486; The unplug the cable can become a floating antenna that can receive noise. If the cable receives a differential noise of more than 10mv, the receiver may be regarded as a valid signal and switch. In order to ensure that any noise is considered a co -mode rather than a differential, a balanced interconnection should be used. The twisted cable will provide a better balance than a flat band -shaped cable.

2. Enter short circuit. If the receiver inputs a short -circuit failure, which causes the 0V differential input voltage, the BLVDS output will remain in a high state. Short -circuit input fault protection voltage range is 0 to 2.4 volts.

3. External pressure. External low -value upper pull and drop -down resistors (for stronger bias) can be used to improve fault safety when there is a higher noise level. The pull -down and drop -down resistance should minimize the range of the load and waveform distortion of the drive and waveform distortion of the driver. The co -mode bias point should be set to about 1.2V (less than 1.75V) to be compatible with internal circuits. For more information, please refer to the application instructions AN-1194 Fault Protection of LVDS Interface .

Physical dimensional inches (millimeters), unless there are other instructions.