Features

● Power:+2.7V to+5.5V

● Micro -power operation: 950 Weian at 5 volts

● 16 -bit monotonous over -temperature

● Setting time: 10 μs to ± 0.003%fsr

● Ultra -low communication string disturbance: --100db typical value

] ● A large output buffer in the tablet with rail -to -orbit operation

● Dual buffer input architecture

● Synchronous or sequential output update and power outage

● Channel broadcast capability [ 123]

● Schmidt trigger input

● TSSOP-16 pack

● Portable instrument

]

● Process control

● Data acquisition system

● programmable attenuation

● PC peripheral device

DAC8534

is a four -channel, 16 -digit module converter (DAC), which provides low -power operation and flexible serial host interface. The precision output amplifier on each film allows the rail -to -rail output swing within the power supply range of 2.7V to 5.5V. The device supports standard 3 -line serial interface, which can enter the data clock frequency of up to 30MHz when IOVDD 5V.

DAC8534 requires an external reference voltage to set the output range of each DAC channel. The device also includes a power -on reset circuit that ensures that the DAC outputs the DAC at zero -scale power and keeps it until it is effectively written. DAC8534 provides a power off function per channel. Through serial interface access, the current consumption of each channel at 5V at 5V is reduced to 200NA.

The low power consumption of the device during normal operation is very suitable for portable battery power supply equipment and other low power consumption applications. At 5V, the power consumption is 5MW. In the power -off mode, the power consumption is reduced to 4μW.

DAC8534 is encapsulated by TSSOP-16, and its working temperature range is -40 ° C to+105 ° C.

Serial writing operation

Typical features

TA +25 ° C ,Unless otherwise indicated.

Operation Theory DAC part The structure of each channel of the DAC8534 consists of a resistance string DAC and an output buffer. Figure 1 shows the simplified box diagram of the DAC architecture. The input encoding of each device is single -polarity, so the ideal output voltage is given by the following formulas:

Among them, D the decimal values of the binary code loaded to the DAC register; its range from 0 to 65535.

Voutx refers to channel A or through D.

Resistance string

The resistance string section is shown in Figure 2. It is just a string of resistors behind 2 resistors. The code loaded to the DAC register is determined to be distributed on which node on the serial. Then, the voltage is applied to one of the switches that connect the serial to the amplifier, and the voltage is applied to the output amplifier.

Output amplifier

Each output buffer amplifier can generate rail circulation voltage on its output, and its output range is close to 0V to AVDD (the gain and offset error must be considered). Each buffer can drive the load of 2K and transmit a 1000PF load to GND. The source of the output amplifier and the ability of the trap can be seen from the typical characteristics.

Serial interface

DAC8534 uses 3 -line serial interfaces compatible with SPI (synchronization, SCLK and DIN) #8482;, QSPI #8482;, and Micril #8482; Interface standards, and most DSPs. For examples of typical writing sequences, please refer to the sequential drawing of serial writing.

The writing order starts from the low level of the synchronous line. The data from the DIN line is sent to the 24 -bit displacement register by the clock to each drop edge of SCLK. The serial clock frequency can be as high as 30MHz, which makes DAC8534 compatible with high -speed DSP. On the 24th decrease of the serial clock, the last data bit was recorded in the displacement register, and the displacement register was locked. Further clocks will not change the shift register data. Once 24 bits are locked to the displacement register, 8msb is used as a control bit, and 16LSB is used as data. After receiving the 24th clock decrease edge, DAC8534 decoded the 8 control bit and 16 data bit to perform the required functions without waiting for the synchronous rising edge. A new SPI sequence starts with the next decline of Sync. Before the 24 -bit sequence is completed, the SPI interface will be reset at the same ascending edge; data transmission will not occur.

At this point, the synchronization line can remain at a lower level or at a high level. In any case, from the shortest delay time to fall on the 24th, the edge of the SCLK must be met to the next decreaseIn order to start the next cycle correctly. In order to ensure the minimum power consumption of the equipment, pay attention to the digital input level as close to each guide as possible. (For the transmission characteristic curve of power current and logic input voltage , see the typical features section.)

IOVDD and voltage converter

IOVDD pins to dic8534 digital input structure power supply power supply power supply supply Essence For single power operations, you can connect to AVDD. For dual -power operations, the IOVDD pin provides interface flexibility for various CMOS logic series, and should be connected to the system logic power supply. DAC8534's analog circuits and internal logic use AVDD as a power supply voltage. External logic high input is converted into AVDD through the level shift. These levels shifts use IOVDD voltage as a reference to convert the input logic high level to AVDD. Regardless of the AVDD voltage, IOVDD can work within the voltage range of 2.7V to 5.5V, which ensures compatibility with various logical series. Although it is specified in 2.7V, IOVDD will work at a voltage of as low as 1.8V, and the time and temperature performance will be reduced. In order to reduce power consumption, the logical VIH level should be as close to IOVDD as much as possible, and the logical VIL level should be as close to the GND voltage as much as possible.

Input displacement registers

The input shift register (SR) of DAC8534 is 24 bits, as shown in Figure 3, which is shown in Figure 3, which is shown in Figure 3. Composition (DB0-DB15). The first two control bits (DB22 and DB23) are address matching. DAC8534 provides additional hardware support addressing capabilities, allowing a single host to communicate with up to four DAC8534 through a SPI bus without any adhesive logic to achieve up to 16 channels. The state of DB23 should be matched with the state of PINA1; similar to the state of DB22 should match the state of PINA0. If it is not matched, DAC8534 will ignore the control command and data (DB21 ... DB0). In other words, if there is no matching, the address is not found DAC8534. The address matching can be covered by broadcasting, as described below.

LD1 (DB20) and LD0 (DB21) use the specified 16 -bit data value or power off command to control the update of each analog output. DB19 is a unwilling bit. It does not affect the operation of DAC8534, which can be 1 or 0. DAC channel selection bit (DB17, DB18) controls the destination from DAC A to DAC D (or power off command). The final control bit PD0 (DB16) selects the power -off mode of the DAC8534 channel.

DAC8534 also supports many different loading commands. The loading command includes a broadcast command to all DAC8534 on the SPI bus. The loading command can be summarized as follows:

DB21 0 and DB20 0: Single channel storage. The temporary register (data buffer) corresponding to DB18 and DB17 is updated with SR data (or power off) content.

db21 0 and db20 1: single channel update. Temporary registers and DAC registers corresponding to DB18 and DB17 are updated for the content of SR data (or power off) in DAC and DAC registers.

DB21 1 and DB20 0: Synchronous update. A channel selected by DB18 and DB17 is updated with SR data. At the same time, all other channels are updated (or power off) with previously stored data.

DB21 1 and DB20 1: Broadcast update. Regardless of whether the address matching or not, all DAC8534 on the SPI bus will respond. If DB18 0, SR data will be ignored, and all channels from all DAC8534 will be updated (or power out of power) with previously stored data. If DB18 1, all channels of all DAC8534 in the SR DATA (or power off) update system. This broadcast update function allows up to 16 channels at the same time.

Power off/data selection is as follows:

DB16 is a power -off mark. If this logo is set, the DB15 and DB14 select one of the four power -off modes of the device described in Table I. If DB16 1, the DB15 and DB14 no longer represent the two MSBs of the data, which represent the power -off conditions described in the table i. Similar to data, the power -off condition can be stored in the temporary register of each DAC. You can use data, power outage or two combinations to update DACs at the same time.

For more information, please refer to Table II.

Synchronous interruption

In the normal writing sequence, the synchronization line is kept low at least 24 decrease along the SCLK, and in the 24th of the 24th Decrease DAC register along the update addressing. However, if the synchronization rises before the 24th decline, it acts as the interruption of the writing sequence; the displacement register is reset and the writing sequence is discarded. The content of the data buffer, the update of the content of the DAC register, and the changes in the operation mode will not occur (see Figure 4).

Powering reset

DAC8534 contains the power -on reset circuit and control the output voltage during the power -power period. When power is powered, the DAC register is full of zero, and the output voltage is set to zero scale; they are kept there until the corresponding DAC channel is issued to effectively write the sequence and the loading command. This is very useful in the application of each DAC output state in the process of power power. Before the device is powered on, the equipment should not be tuned high.

Power off mode

Use four operating modes of DAC8534. passSet three -bit (PD2, PD1, and PD0) in the displacement register and perform loading operations on DAC to access these modes. DAC8534 provides a very flexible power -off interface based on channel register operation. The channel is a single 16 -bit DAC, temporary storage register (TR), and DAC register (DR) with a single power -off circuit. TR and DR are 18 -bit. The 16 -bit TR and DR can temporarily store 16 -bit and 16 -bit data. Internal circuits ensure that when DB16 1, DB15 and DB14 are transmitted to TR17 and TR16 (DR17 and DR16).

DAC8534 regards the power -off condition as data, and all operating modes are still effective for power off. You can broadcast the power condition to all DAC8534 in the system, or you can close the channel while updating the data on the other channels.

DB16, DB15, and DB14 100 represent the Hi-Z output impedance conditions of the selected channel. 111 is the same. 101 represents a power -off condition with an output impedance of 1K, and 110 indicates that the output impedance is 100K power -off conditions.

When both bits are set to 0 or 1, the device enters a high impedance state, and the typical power consumption at 5V is 3Pa. However, for the two low -impedance output modes, the power supply is reduced to 100NA at 5V (50NA at 3V). Not only did the power current decrease, but the output level also switched from the output of the amplifier to the well -known resistance network. This has an advantage, that is, in the power -off mode, the output impedance of the device is known. There are three different options for power failure: the output is connected to the GND inside 1K resistance, 100k the resistance is connected to the GND, or the road is kept (high impedance). The output phase is shown in Figure 5.

When the power shutdown mode is activated, all analog circuits are closed. When the PD0 is set to 0, each DAC will exit the power, the new data is written into the data buffer, and the DAC channel will receive the load command. For AVDD 5V, the time to exit power is usually 2.5 μs; for AVDD 3V, the time to exit power is usually 5 μs (see typical features).

LDAC function

DAC8534 provides software and hardware to update functions. The design of the DAC8534 dual buffer structure allows each DAC to enter new data without interference the simulation output. Software synchronization updates are controlled by Load 1 (LD1) and LOAD 0 (LD0). By setting Load 1 to 1 , all DAC registers will be signal at the 24th clock. When the new data is input into the device, all DAC outputs can be updated synchronously with the clock.

The internal DAC register is triggered by the edge, not a horizontal trigger. Therefore, when the LDAC pin signal is converted from low to high, the number in the DAC input register is currently locked. In addition, it allows to write the DAC input register at any time; then, the DAC output voltage can be changed through the LDAC pin. LDAC triggers can only be used after the buffer is correctly updated by the software. If you only want to update the DAC output through the software, the LDAC pin must be permanently tied to a low position.

Micro -processor interface

DAC8534 to 8051 interface

DAC8534 and typical 8051 microcontroller are shown in Figure 6. The interface settings are as follows: 8051's TXD driver DAC8534 SCLK, RXD driving serial data cable.

Synchronous signal comes from a programmable pins on Port 8051. In this case, use the end port P3.3. When the data is transmitted to DAC8534, P3.3 is low. 8051 transmits data with 8 -bit bytes; therefore, only 8 clocks in the transmission cycle have decreased. In order to load the data to DAC, after the first 8 digits are sent, P3.3 remains low, and then starts the second and third writing cycle to transmit the remaining data. P3.3 takes high after the third writing cycle is completed. 8051 In the first display of LSB format output serial data, DAC8534 requires that its data is the first place in receiving. Therefore, the 8051 transmission program must consider this and mirror data as needed.

DAC8534 to Micro -Line interface

Figure 7 shows the interface between DAC8534 and any Microwire compatible device. The decline of serial data was shifted along the line of the serial clock, and the rising edge of the CK signal was sent to the DAC8534 by the clock.

DAC8534 to 68HC11 interface

Figure 8 shows the serial interface between DAC8534 and 68HC11 microcontrollers. 68HC11 SCK driver DAC8534 SCK, while MOSI output drives the serial data cable of DAC. Synchronous signal comes from the end port (PC7), similar to the 8051 chart.

The 68HC11 should be configured, so that the CPOL bit is 0 and the CPHA bits are 1. This configuration makes the data displayed on the MOSI output valid on the decrease of SCLK. When the data is transmitted to DAC, the synchronization line is kept at low (PC7). Serial data from 68HC11 is transmitted in 8 -bit bytes, and only 8 clocks in the transmission cycle drop. (Data is first sent to MSB.) In order to load the data to DAC8534. After the first 8 digits were transmitted, the PC7 remained low, and then the DAC executed the second and third serial writing operations. PC7 takes a high value at the end of this program.

DAC8534 to TMS320 DSP interface

Figure 9 shows the connection between DAC8534 and TMS320 digital signal processor (DSP). A DSP can control up to four DAC8534 without any interface logic.

Application

current consumption

DAC8534 usually consumes 250 μA when AVDD 5V, and consumes 225 μA when AVDD 3V, including reference reference Current consumption. If vih lt; lt; IOVDD, additional current consumption may appear in digital input. For the most effective power operation, it is recommended to use the CMOS logic level at DAC's digital input terminal.

In the power -off mode, the typical current of each channel consumes 200NA. The delay time of 10 ms to 20 ms after sending a power off command to DAC is usually sufficient to reduce the electric current to less than 10 μA.

Drive resistance and capacitor load

DAC8534 output level can drive up to 1000PF load while maintaining stability. In the range of offset and gain error, when the capacitance load is driven, the DAC8534 can operate the rail. The resistance load of 2K can be driven by DAC8534, while achieving a typical load adjustment of 1%at the same time. When the load resistance drops to 2K below, the load adjustment error increases. When the output of the DAC is driven to the right track under the resistance load, the PMOS transistor in each AB output stage can enter the linear area. When this happens, the increased infrared voltage drop will deteriorate the linear performance of DAC. This occurs only about the output voltage characteristics of about 20 millival DAC. If a good linear is required at a full range (under the resistance load conditions), the reference voltage for DAC8534 can be reduced to the power supply voltage for AVDD to eliminate this situation.

String and AC performance

DAC8534 architecture is the use of a separate resistance strings for each DAC channel to achieve ultra -low stringing performance. During the full label change of the adjacent channel, the DC disturbances seen on a channel are usually less than 0.5LSBS. The measured interchange skewers (for the full standard of 1kHz sinusar wave output on one channel, measurement on another output channel) is usually lower than -100dB. In addition, DAC8534 can realize the typical communication performance of 96DB SNR (signal -to -noise ratio) and 65DB THD (total harmonic distortion), making DAC8534 a reliable choice for high signal -to -noise ratios to require high signal -to -noise ratios at 4KHz or below output frequency.Essence

Output voltage stability

DAC8534 has good temperature stability. Within the specified temperature range of the device, the typical output voltage drift is 5ppm/° C. This allows the output voltage of each channel to remain within the range of ± 25 μV within the range of the environmental temperature change range of ± 1 ° C.

A good power suppression ratio (PSRR) performance reduces the power noise on the AVDD from the output to 10 μV-S. Combining good DC noise performance and real 16 -bit differential lineivity, DAC8534 has become an ideal choice for closed -loop control applications.

Stable time and output failure

For the full scale code of the input, the stable time within 16 -bit accurate range of DAC8534 can be achieved within 10 μs. In the worst case, the setting time between continuous code changes is usually less than 2 μs, so that the update rate of digital input signals is as high as 500KSPS (converting code to code). DAC8534's high -speed serial interface is designed to support these high updates.

For the output oscillating of the full marked scale, when the 200PF capacitance load is driven, the output level of each DAC8534 channel usually shows excess and lower rushing of less than 100mV. Because the conversion of code to code does not span the boundary of the NX4096 code, the change from code to code is very low. Due to the internal section of the DAC8534, a small failure of code to code occurs at each intersection of the NX4096 code boundary. When n 15, these faults may be close to 100NVS, but resolved within ~ 2 μs.

Using REF02 as a power supply for DAC8534

Since DAC8534 requires a very low power current, a possible configuration is to use the REF02+5V precision reference voltage to provide DAC8534 power supply input and reference input input input and input input The required voltage, as shown in Figure 10. If the power noise is large or the system power supply voltage is not 5V, this is particularly useful. Ref02 will output a stable power voltage for DAC8534. When the current is 855 mAh, it is also necessary to input the current to the current to 855 mAh, so that the current is needed to input the current to a current of 0.855 mAh. The total typical current required (the DAC output has 5K load) as:

Billar operation of DAC8534

DAC8534 design It is used for single -power operation, but the circuit in Figure 11 can also achieve bipolar output range. The output voltage range of the circuit shown is ± VREF. Using the amplifier (such as OPA703) can realize the rail operation of the amplifier output terminal, as shown in Figure 11.

Any input codeThe calculation of the output voltage is as follows:

Among them, D represents the decimal input code (0 --65535).

VREF 5V, R1 R2 10K :

The output voltage range is ± 5V, 0000h corresponds to -5V output, FFFFH corresponds to the corresponding corresponding Output in+5V. Similarly, using VREF 2.5V can achieve the output voltage range of ± 2.5V.

Layout

A precise simulation element needs to carefully layout, enough bypass, and clean and good power supply.

DAC8534 provides single -power operation, usually with digital logic, microcontroller and, microprocessor and digital signal processor. The more digital logic in the design, the higher the switch speed, the more difficult it is to prevent digital noise on the output end.

Due to the single -connected pins of the DAC8534, all the return (including DAC's numbers and simulation circuit currents) must flow through a single point. Ideally, GND will be directly connected to the simulation ground layer. The plane is separated from the grounding connection of digital components until they connect to the power entrance of the system.

The power supply applied to AVDD should be well adjusted and low in noise. Switching power and DC/DC converters usually generate high -frequency faults or peaks on the output voltage. In addition, digital components can generate similar high -frequency peaks in its internal logical switch state. This noise can easily be coupled to the DAC output voltage through the various paths between the power connection and the output.

Like GND, AVDD should be connected to the positive power plane or trace line separated from digital logic, until they are connected at the power connection point. In addition, it is strongly recommended to connect 1 μF to 10 μF capacitors with 0.1 μF bypass power container. In some cases, additional bypass may be needed, such as 100μF electrolytic capacitors, and even the PI filter composed of electrical and capacitors. Essence

A SPI bus can use up to four DAC8534 devices without any adhesive logic to create high -channel counting solutions. When using multiple DAC8534, you need to pay special attention to avoid digital signal integrity. The same SPI bus. As long as the rising time of these digital signals is greater than the delay of transmission between the two DAC8534 devices, the signal integrity of the Sync, SCLK and DIN lines will not be a problem. The propagation speed of the standard printing circuit board is about 6 inches/nan seconds. Therefore, if the number of digital signals rising is 1NS, it is recommended that the distance between any two DAC8534 devices does not exceed 1 inches. If DAC8534S must be farther on the PCB, it should be put throughSet the series Resi to shorten the signal rising time-synchronization, SCLK and DIN line driver TOR.If the maximum distance between any two DAC8534 must be 6 inches, the rising time should be reduced to 6 nano seconds. The series resistors on the digital drive and the total tracking and input capacitance RC network on the digital drive.

Mechanical data

Note: A. All linear size units are all millimeters.

B. This drawing will not be notified separately if there is any change.

C. The main size does not include mold flying or protruding objects with no more than 0.15.

D. It belongs to Jedec Mo-153.