The current mode control PWM

The switching frequency is as high as 1MHz

Low the start current ( lt; 120 μA)

It is suitable for large current output drive

Power MOSFETT (1A)

Full locking PWM logic with dual -pulse inhibitory

The programmable duty cycle

100%and 50%maximum duty cycle limit

[

123] Spare function

Available soft startup

Over -current fault detection and restart delay

Pwm UVLO

input/output Synchronous

Locking for disable

current response internal 100ns cutting edge blank blank

Packag The technology developed in BCD60II has been designed to control the use of a fixed frequency current mode. Based on the standard current mode PWM control device, this device has the following characteristics that can be programmed and softened, input and output synchronization, disabled (for overvoltage protection and for power management) Limited, soft -by -current protection with soft start intervention, and light loading of spare function torquers with reduced oscillator frequency.

Electric characteristics (VCC 15V; TJ 0 to 105 ° C; RT 13.3K (*) CT 1NF; unless there are other regulations.)

RT RA // RB, RA RB 27K

Electric characteristics (continued)

Spare function

The spare function can automatically detect the light load state and reduce the frequency of the oscillator. When the output load increases and exceeds the defined threshold, the frequency is automatically recovered. This function allows minimizing power loss related to the switching frequency. The switching frequency represents most of the loss in light load and rejuvenation, and OUT abandons the frequency of the higher switching advantages when loading. This is the peak current by monitoring linearly related error amplifiers (VCOMP), except offset. If the peak current is reduced (as a load) and VCOMP is lower than the fixed threshold (VT1), the oscillator frequency will be set to the lower limit (FSB). When the peak of the current increases and the VCOMP exceeds the second threshold (VT2)The oscillator frequency is set to normal value (FOSC). Proper lags (VT2-VT1) to prevent accidental frequency change power to make VCOMP close to the threshold. This operation is shown in Figure 21. Normal frequency and spare frequency are external programming. VT1 and VT2 are fixed with each other, but the threshold can be adjusted according to the input power level.

Application information

Detailed pins function description

needle pin 1. Synchronous (input/output synchronization). This function allows IC oscillator to synchronize other controllers (main controllers) or to be synchronized to the external frequency (from). As the main pulse, the pin is passed on the positive pulse of the oscillator (see pin 2). Triggered at the edge of the subordinate operation circuit. Reference is shown in Figure 23. When several IC parallel work does not have the designated needs, because the fastest one automatically becomes the main control. During the rise of the oscillator's slope, the pins were pulled down by the leakage current of the 600 μA. At the edge of the decrease, the pulse is released, and the 600μA is turned off and cut off. The power of a generator is usually 7 mAh (the voltage is still higher than 3.5V).

In FIG. 22, some practical examples of synchronous L5991 were given. Because the device will automatically reduce its operating frequency under light load conditions, reasonable assumptions that synchronous operations will be operated normally, not backup. Needle 2. RCT (oscillator). Two resistors (RA and RB) and a capacitor (CT), as shown in Figure 23, allow the working frequency (FSB) of the operating frequency (FOSC) of the oscillator during normal working (FSB). CT is charged from VREF through RA. When running normally (standby high), it is only standby (standby low) from RB charging through RB. See Pink 16 to show how to generate a spare signal. When the voltage on the CT reaches 3V, the capacitor is quickly discharged. As a voltage voltage drop to 1V, it started charging again.

The oscillating frequency can be used

to use the chart in Figure 14, where RT will be with RA under normal circumstances. Run parallel to RB and RT RA is in a spare state, or consider the following similar relationship:

Gives normal operating frequency, and:

This is the spare frequency

Torch transformer will work at light load. In the above expression, RA // RB said:

and the duration of the decline edge:

[] TD is also a synchronous pulse transmitted by a needle. The duration defines the duty cycle range DX (DX defines shots 15 and calculations) because the output is maintained at a low level when the decrease edge. However, if V15 is connected to VREF, the switching frequency is one of the values.By semi -based on Figures 14 or (1) and (2). To prevent the frequency of oscillator from switching from FOSC to FSB back and forth, the ratio of FOSC/FSB must not exceed 5.5.

During the normal operation period, the IC will choose the frequency lower than the FOSC (usually 10-20%) in any case with the external oscillator, RA, RB, and CT synchronization. Try tolerance. Needle 3. DC (duty duty control). Performing this needle -pin voltage between 1 and 3 V is possible to set the maximum duty ratio at 0 and upper limit DX (see pin 15). If DMAX is the maximum duty ratio required, the voltage V3 applied on the pin 3 is:

internal comparative comparison of the internal comparison between the V3 and the oscillator slope (see Figure 24), Figure 24), Figure 24),, Figure 24),, Figure 24). Therefore, if the device is synchronized with the external frequency FEXT (therefore, the amplitude of the oscillator is reduced), (5) becomes:

A voltage below 1V will inhibit the drive output. This device cannot be lock -up and disable, such as under overvoltage protection (see application concepts). If there is no need to limit the maximum duty ratio (ie dmax dx), the sales must keep floating. Internal pull (see Figure 24) can keep the voltage above 3V. If you insert the noise (for example, during the ESD test), it can be connected to VREF through 4.7k resistors.

needle 4. VREF (reference voltage). The device is to provide accurate voltage benchmark (5V ± 1.5%) that can transmit some milliam circuits to the outside. Small film capacitors (a typical value of 0.1 μF), connected between the pin and SGND, it is recommended to ensure the stability of the generator and prevent the noise that affects the benchmark. Before the device starts, the leakage current of the pin is about 0.5mA.

Pink pin 5. VFB (error amplifier reverse input). This feedback signal is applied to this pin and compared with E/A internal reference (2.5V). This E/A output generates a control voltage correction ratio. E/A uses high -gain bandwidth products, which can broaden the overall control loop, high conversion rate and current capability, and improve its signal characteristics. Generally, the compensation network that stabilizes the entire control loop is connected between the pin and COMP (pin 6).

Pin pin 6. Comp (error amplifier output). Generally, this pin is used for frequency compensation and related network connections between the two and VFB (pin 5). Since L5991, the compensation network cannot ground E/A is a voltage mode amplifier (low output impedance). For some tests about compensation technology, please refer to the application idea. It is worth mentioning that some values u200bu200bof the compensation network must be calculated into the exchange count of spare frequency. In particular, this means that the frequency of the cross -loop crossing must not exceed FSB/4 ÷ FSB/5. Monitoring pin 6 voltage to reduce the frequency of the oscillator when the converter works (reserve)Essence

Pinper 7. SS (soft start). When the device starts, connect to the pin and SGND (pin 12) charging generator from the internal current, ISSC, up to 7 volts. During this period, the E/A output was restrained by the voltage through the CSS itself, allowing linearly to rise, starting from scratch to the stable state value given by the control loop. The maximum interval time during the E/A clamping period, the reference soft startup time is about:

in the formula, RSENSE is a current fluid resistor (see needle pin 13). IQPK is the peak current of the switch (the flow is determined to be depends on Load at NSE). Usually, for TSS, the choice of CSS is usually milliseconds. As mentioned earlier, the soft startup intervention can also be used for severe overload or short -circuit output. Refer to Figure 25. The pulse current is limited to some extent. It is effective to some extent. As long as

can reduce the connection time of the power switch (from A to B). After the shortest connection time is reached (starting from B), the current is controlled. To prevent this risk, the comparator triggered the current processing program, called the ""HICCUP"" mode when the voltage was higher than 1.2V (point C) (Isen, pin 13). Basically, the IC is closed, and then the soft start is just detected. As a result, the operating point suddenly moved to D, and the folding effect was created. Figure 26 shows the operation. When a permanent failure, the oscillating frequency appears on the soft startup capacitor. The reference is ""snoring"" as the cycle, about

Since the system will try to restart each failure cycle, there is no risk of lock lock risk. Essence The ""snoring"" causes the system to be controlled to prevent short circuits, but it cannot eliminate the stress of the power element during the period of pulse limit (from A to C). If you can better control overloads, other external protection circuits are required.

Pink pin 8. VCC (controller power supply). This needle provides a signal part of an integrated circuit. The device can be enabled as the VCC voltage exceeding the starting threshold and as long as the voltage is higher than the UVLO, it can work threshold. Otherwise, the device will be closed and the current consumption will be extremely low ( lt; 150 μA). This is to reduce the consumption of the starting circuit (only one resistor), which is the most important contribution to the power loss of power loss. The internal Ziner limits the voltage on the VCC to 25V. If this limit is exceeded, the IC current consumption will increase significantly. A small film capacitor (needle feet 12) between this pin and SGND is as close to the IC as much as possible to filter high -frequency noise.

Pink pin 9. VC (power -level power supply). IT supply the drive of the external switch, so AB absorbs pulse current. Therefore, it is recommended that 11 -needle capacitors (PGA, as close as IC) can maintain commotion in order to avoid these current pulses. This pin can be connected to the buffer power container directly or through the resistor, as shown in Figure 27, control the speed of the external switching of the switch, usually the power MOS. During the drive, the gate resistance is RG+RG ', and the AT shutdown is limited to RG.

needle foot 10. Output (drive output). This pins are the output switch of the external power drive level. Generally, this will be a power MOS, Al, although the power of the driver is enough to drive BJT (1.6A source, 2A exchange, peak). The driver consists of a totem rod and a high -side NPN Dallingon and a low -side VDMOS, so there is no need to clamp the external diode to prevent the voltage from being lower than the ground. The internal clamping is limited to 13V transmission to the gate voltage. Therefore, it can be provided with a higher -voltage drive (pin 9), without any damage to the oxidation layer of an external MOS grid oxide. Piece does not cause the power consumption inside the chip, because the current peak of the door charge appears in the gate voltage, and the clamping is not positive. Moreover, when the gate voltage is 13V, it is steady. Under UVLO conditions, internal circuits (as shown in Figure

In Figure 28), in order to ensure that the external power supply cannot be turned on. This circuit is characterized by the same receiver capacity (usually 20mA@1V) from VCC 0V to the startup threshold. When the threshold is exceeded, L5991 starts to work, and VREFOK is pulled up (reference picture. 28) and the circuit is disabled. Then you can omit the ""deflection"" resistor (connected between the door and the source (MOS) is usually used to prevent the connection of an unpopular external MOS because some leakage current

Needle 11.PGND (Power grounding). The current circuit is closed through this pin during the discharge of the external gate. This cycle should be as short as possible to reduce the separation of electromagnetic interference and operation and signal current.

needle pin 12.SGND (signal grounding). This grounding refers to the control circuit of the integrated circuit, so the grounding connection of all related external components must be controlled, and this pin must be led to. In addition to PCB, you must pay attention to prevent from from obeying from from PCB. Flowing through the SGND path.

needle 13.isen (current feeling). (IQ) Image. When the voltage is equal: The switching of the switch is terminated. In order to increase the resistance, a ""cord"" with a ""leading advantage of about 100NS"" is realized internally as shown in Figure 29. Therefore, the smoothness of this smoothness. The RC filter between the pin and the RSENSE can be moved again, or at least it can be greatly reduced.

needle graf 14. Dis (device disable). When the voltage rises to 2.5V above 2.5V, the IC closure needs to be closed. Pull VCC (IC power supply voltage, pin 8) is lower than the UVLO threshold to allow the device to restart. The pin can be driven by the external logic signal to the power management of the power supply, as shown in the figure.30 can also achieve overvoltage protection. If the ""Application"" section shows it, use a filter capacitor to connect this pin to the ground to avoid peaks due to noise. If not, it must be connected to the Chinese.

Pin pin 15. DC-LIM (maximum duty cycle limit). The upper limit of the duty cycle range depends on the voltage applied to the pin. Almost,

If DC-LIM is grounded or kept floating. Instead of

The output switch will be halved

About the oscillator, because the internal T trigger (see Fragments) were activated. Figure 31 shows the operation. The discharge of the timing ratio option to accelerate the timing capacitor CT (for the duty cycle to be close to 50%as much as possible), so the frequency of the oscillator-at the same timing element, the frequency will be slightly higher.

pin 16. S-by (standby function). The resistor RB, set the oscillator normal work (FOSC) with RA. In fact, as long as the spare signal is high, the pin is connected to the reference voltage VREF connected N -channel field effect transistor (see Figure 32) through the following method (see Figure 32), so the timing capacitor CT is charged through RA and RB. when? When the spare signal is reduced, the sales will float when the transistor is closed. RB is

Now disconnect, CT is only charged through RA. The frequency of the oscillator (FSB) will be lower. Refer to the needle pin 2 to understand how to calculate the timing component. The typical values u200bu200bof VT1 and VT2 are 2.5 V and 4 V. This 1.5V lag is sufficient to prevent frequency changes from changing the ratio of 5.5 and 1 FOSC/FSB. The value of VT1 makes the input power of about 13%. If necessary, the power can be reduced by adding a threshold of the DC offset (VO) below 13%on the current influenza response pin (13, Isen). This will also allow frequency changes greater than 5.5 to 1. The following formulas are applicable to design:

Among them When the power is higher than this value, L5991 will switch from #402; SB to the primary inductance of #402; OSC and LP rejuvenation transformer. Connect to VREF or keep this pin open the unused spare function in the following cases.

Layout Tips

Generally speaking, the correct circuit board layout is critical to the correct operation, but it is not easy. Be careful to place components, correct wiring, and appropriate trace width. If high voltage, it meets the main problems of the isolation distance. L5991 By using the two pins for separate current bias (SGND) and openingThe back -driven current return (PGND) is very complicated, and only a few important issues will be reminded here.

(1) All current returns (signal grounding, power supply ground, shielding, etc.) shall be wiring separately, and only a single location.

(2) The noise coupling can be limited by the minimized current ring.This is particularly suitable for high pulse circuit water flow.

(3) For the high current path, it should be on the other side of the PCB: this will reduce the two resistance and the inductance of the line.

(4) Magnetic field radiation (and mixed inductance) can reduce the switching current as short as possible by retaining all traces.

(5) Generally speaking, the trajectory of carrying signal current should be far away from the traces of the pulse current or the voltage of the voltage.From this view, you should be particularly careful of high impedance points (current influenza input, feedback input, etc.).It may be a good idea on the PCB side and the other with power sources.

(6) Points of some important circuits, such as reference voltage, IC power pins, etc.