Output capacitor

Because the microprocessor requires a current change of more than 50A when the microprocessor is carried out, and the output capacitor is a basic component for the rapid response of the power supply. Due to the faster response of the load, the dual -access reduces the required output capacity (the switching frequency of the load connection is doubled). Elimination of current ripples caused by 180 ° phase shifts also reduces the requirements for output ESR between the two phases to maintain the specified voltage ripple. When the load transition is used to the output of the converter, the load current is provided by the output capacitor within the initial microfinance. The controller immediately identifies the load transient and increases the load cycle, but the current slope is limited by electrical value. Due to the current changes in the capacitor (ignore ESL): #8710; vout u003d #8710; IOUT · ESR

During the load transient state, a minimum capacitor value is required to maintain the current without discharge. The voltage caused by the discharge of this output capacitor can be concluded through the following formulas:

Among them, DMAX is the maximum duty cycle. The lower the ESR, the lower the output during the load and the lower the static ripple of the output voltage.

inductor design

The inductance value is defined by the compromise between the transient response time, efficiency and cost. The inductor must be calculated to maintain the output and maintain the input voltage change ripple current #8710; IL between 20%and 30%of the maximum output current. The inductance value can be calculated through the following relationship:

Among them, the FSW is the switch frequency, VIN is the input voltage, and VOUT is the output voltage. Increasing the electrical value will reduce the ripple current, but it will also reduce the transient response time of the converter load. The response time is that the time required for the electrical sensor to change the current from the initial value to the final value. Since the inductor has not completed the charging time, the output current is output capacitor. The minimum response time can minimize the required output capacitance. The response time of the load transient state is different due to the application or removal of the load: if the load is applied, the inductor is equivalent to the voltage charging voltage between the input and output. During the disassembly process, it only discharge from the output voltage. The following expression gives the compensation network response fast enough #8710; i load transient approximate response time:

The worst situation depends on the available situation depends Input voltage and selected output voltage. In any case, the worst case is the response time after the load removal, the minimum output voltage is programmed, and the maximum input voltage is available.

The main control loop

Control circuit's measuring control loop and average current mode control circuit. Each circuit is corrected to PWM under the circumstances of an appropriate gain to reduce its adjustment error toThe lowest: the balanced inductor current of the measuring flow control loop, the average current mode control the fixed output voltage of the loop is equal to the reference voltage of VID programming. Figure 13 reports the main control loop.

Uniform (CS) Control loop

Performatial flow is the average current mode control scheme using transformer to conduct information to divide the large amplifier information. Built -in one of the current of reading current average (IAVG); the error between the reading current and the benchmark is converted into an appropriate gain voltage to adjust the duty cycle. The amplifier settings (see Figure 14). The balance control is a high -bandwidth control circuit, which is allowed to flow even during the load transient. The equal flow error is affected by the selection of external components; the precision RG resistance (± 1%is the necessary) induction current. The uniform flow error is divided into large vessels in the control of the transformer voltage offset in the internal transformer. Considering that the voltage offset of the sensing resistance is equal to 2 millivolves, the current reading error is given by the following formula:

In the formula in the formula #8710; IREAD is the difference between single -phase current and ideal current (IMAX/2). For RSENSE u003d 4M and IMAX u003d 40A, the equal flow error is equal to 2.5%, and the ignore is not matched by RG and RSENSE.

ACM control circuit gain design to obtain a high DC gain, to maximize the static error and span the 0db shaft as a slope to -20db/dec, the expected cross frequency is to be the cross frequency of the expected cross frequency ωt. Ignore the impact of ZF (S), then there is one zero pole and two poles that pass the transfer function. Once the output filter is designed, the two poles are fixed zero zero and drooping resistance. In order to obtain the required shape, ZF (S) implemented the RF-CF series network. Zero -degree and then introduce ωf u003d 1/RFCF and integral device. The zero point corresponding to the maximum of the static error and the resonance of the L-C at the maximum of this integror is -20dB/DEC's simple gain shape (see Figure 15) 1. In fact, considering the usual value of the output filter, the result of the LC resonance is that the lower frequency is more zero than the above. The compensation network can simply be designed to ωz u003d ωlc and applied the expected cross -frequency ωt:

layout guide , Layout is one of the most important things to consider when designing this large current application. A good layout scheme can reduce power consumption on the power path, reduce the radius, appropriate connection between signals and power places can optimize the control performance cycle. Integrated power drives reduce the number of components and reduce the interconnection between the control function and the drive, and reduce the circuit board space. Here are the main points to pay attention to the new layout, and the corresponding implementation rules are recommended. Power supplycatch. The current continues to flow from the input terminal to the load. The first priority of the component must be kept to the power segment to minimize each connection as much as possible. In order to minimize noise and voltage peaks (EMI and loss), these connectors must be part of the power supply plane, no matter what, it is achieved by wide copper traces. Key components, that is, power transistors, must be as close to the controller as possible. Considering that the ""electrical"" components reported in the figure consist of more than one ""physical"" component, it is recommended to use ground plane or ""star"" grounding connection to minimize the impact caused by multiple connections.

FIG. 16A shows the details of the power connection and current circuit involved. Input capacitors (CIN)

or at least a part of the total capacitance must be placed in a place near the power segment to eliminate the mixed inductance generated by the copper traces. Low ESR and ESL capacitors are needed. Related power connection. Figure 16B shows the placement of some small signal components, and how to mix signal and power planes. The distance between the driver and the MOSFET gate should be shortened as much as possible. The number and minimization of the voltage peaks generated by the delayed inductance of the copper thread. In fact, the farther the MOSFET is the device, the longer the rotor of the integrated grille. As a continuous sequence, the higher the voltage peak corresponding to the rising and decrease signal of the gate of the gate. Even if these peaks are restrained by the inherent internal diode, delayed propagation, and the potential causes of noise and unstable potential causes are introduced into a harmful system behavior. An important consequence is the significant increase in the loss of high -side MOSFET. Therefore, it is recommended to drive the drive side towards MOSFET, Gatex and Phasex to the high -sides MOSFET together, with a minimum distance (see Figure 17). In addition, because the Phasex pin is the return path of the high -voltage side drive, it must be connected to the MOSFET source of the MOSFET source directly to the high -voltage side. For LS MOSFET, the return path is PGND pins: it can be directly connected to the power ground layer (if it is implemented) or the same way as the source of the LS MOSFETS source. Gatex and PHASEX are connected (and when there is no power ground plane, PGND) must also be designed to handle excessive current peak 2A (the recommended width is 30 dense ears). Several ohm's gate resistance helps reduce the power consumption efficiency of integrated circuits without damage systems.

The placement of other components is also important:

- The guide capacitor must be as close to the Bootx and Phasex pins as much as possible to narrow the circuit created.

- Place VCC and SGND's decoupled power containers at the position closer as close to the related pins.

- Separate the capacitor from VCCDR and PGND, and get closer to thisSome pins. This capacitor maintains the peak current required by the low -side MOSFET drive.

- Refer to all sensitive components of SGND, such as the frequency setting resistor (if.) And optional resistors from FB to GND, to provide positive speed reduction effects.

- Connect the SGNN to PGND (output capacitors) on the load side to avoid bad load adjustment effects without using a remote test buffer, ensuring the correct adjustment accuracy.

- It is recommended to place additional 100NF ceramic capacitors near HS MOSFET. Helps reduce noise.

- Phase pins peak. Because the HS-MOSFET switch is in the hardware mode, high-voltage peaks can be observed

on phase pins. If these voltage peaks exceed the maximum breakdown voltage of the pin, the device can absorb energy and cause damage. The voltage peak must be restricted by proper layout. The gate resistance is used in parallel to the low -voltage side MOSFET and/or cushioning network low -side MOSFET. Under the maximum 600kHz FSW, the value of 20NSEC is lower than 26V.

current influenza response connection

Remote buffer: The input connection of this component must be used as a parallel network from the FBG/FBR route to compensate for the loss along the output power trajectory. noise. Connecting these pins on a point away from the load will cause non -best load adjustment and increase the output tolerance.

current reading: The RG resistor must be as close to the IsenX and PGNDSX pins as much as possible to limit the noise of the injection device. The PCB line must be connected to the reading point as a parallel recorder to avoid picking up any co -model noise. This is also important to avoid any offset in the measurement and get better accuracy. It should be as close to the trace line as possible for sensory elements, special current fluctuation resistors or low -side MOSFET RDSON. In addition, when using a low -side MOSFET RDSON as a current detection element, the IsenX pin is actually connected to the Phasex pin. Do not connect your pins together, and then connect to the HS source! Due to the noise generated when the high -pressure side drive returns, the equipment cannot work properly. In this case, two independent networks: connect Phasex pins to HS source (routing with HGATEX), and sell (30 dense ear) and IsenX to LS drainage pipes (wiring with PGNDSX). In addition, PGNDSX pins are always connected to PGND through the RG resistor: Do not directly connect to PGND! In this case, the device cannot work normally. In any case, it is necessary to ride to the LS MOSFET source (with the IsenX network). The correct and wrong connection is shown in Figure 18. In order to avoid the imbalance between the two phases of the converter, symmetrical layout is also recommended.

Demonstration board description

L6919E demonstration board shows the operation of the device in double use. This evaluation committee allows the output voltage (0.800V-1.550V) and high output current capacity through switching S0-S4. The layout of the circuit board can use up to the maximum flexibility when selecting MOSFET when selecting MOSFET. Considering the following factors, the copper thickness of the four -layer demonstration board is 70 μm to minimize the high current that can be transmitted by the conduction loss circuit. The circuit of the demonstration board is shown in Figure 19.

Multiple jump lines allow different configurations to set the device: JP3, JP4, and JP5 Allow the configuration remote buffer. JP5 just starts JP5 and makes the output short -circuit board voltage; to achieve real remote sensing, keep these jumps disconnect and connect the connectors on the FBG and FBR demonstration boards to connect to the remote load. In order to avoid using remote buffer, you only need to shorten all jump 3, JP4 and JP5. The local perception of R7 is used to regulate. You can use jumper JP1, JP2, and JP6 to configure inputs in different ways; these jumper can also control the MOSFET driving power supply voltage. In short, the power conversion starts from VIN, and the device is powered by VCC (see Figure 20).

It can distinguish between two main configurations: single power supply (vcc u003d vin u003d 12V) and dual power supply (vcc u003d 12V) vin u003d 5V or different).

- Single power supply: In this case, JP6 must be completely short -circuit. This device is equipped with the same guide for conversion. Using additional Qina diode DZ1, you can get a lower voltage. If MOSFET is a logic drive of MOSFET, it can be used. In this case, JP1 must be kept open so that the HS driver provides VIN-VDZ1 through Bootx, and JP2 must be short to the left to use VIN or VIN-VDZ1 to power the LS drive through the VCCDR pin. Otherwise, JP1 must be short -term JP2 to be free to short in these two positions.

- Dual power supply: In this case, VCC directly supply power to the controller (12V), and VIN is used for power conversion for HS drainage pipes. The last one can start from the 5V bus (typical) or other bus that allows the maximum flexibility in power conversion. The power supply of the MOSFET drive can be programmed as shown before, and jumped through JP1, JP2 and JP6. JP6 is now choosing VCC or VIN about requirements. The following Figure 21 and 22 report some examples