TAJD686K020RNJ_TAJD686K020RNJ Introduction

The structure of the N-channel enhancement mode MOS transistor is made on a P-type silicon substrate with a low doping concentration, and two N+ regions with a high doping concentration are made, and two electrodes are drawn out with metal aluminum, which are used as the drain d and the source respectively. pole s. Then cover the semiconductor surface with a thin layer of silicon dioxide (SiO2) insulating layer, and install an aluminum electrode on the insulating layer between the drain and the source as the gate g.

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But there are parasitic diodes between the D pole and the substrate. If it is a single transistor, the substrate is of course connected to the S pole, so there is naturally a diode between the DS. So what does the parasitic diode do? When a large instantaneous reverse current is generated in the circuit, it can be derived through this diode, so as not to break down the MOS tube. (plays the role of protecting the MOS tube). The analog circuit book talks about the structure of low-power MOS tubes, so there is no such diode. If in the IC, the N-MOS substrate is connected to the lowest voltage, and the P-MOS substrate is connected to the highest voltage, which is not necessarily connected to the S pole, so there is not necessarily a parasitic diode between DS.

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] interval, the DS voltage of the MOSFET drops to the same as Vgs, resulting in the Millier effect, the Cgd capacitance increases greatly, and the gate current continues to flow. Due to the sharp increase in the Cgd capacitance, the charging of the gate voltage to Cgs is inhibited, so that Vgs Nearly horizontal, the voltage on the Cgd capacitor increases while the voltage on the DS capacitor continues to decrease.

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