Features

18 channel gamma correction

Available channel vCOM: 100mA output [123 123 ]

OTP memory on the film

10 -bit resolution

Rail -to -track output

Low power current: 900 μA/CH

Power voltage: 7V To 18V

Digital power supply: 2.0V to 5.5V

Industry standard, dual -line interface: 3.4 MHz high -speed mode

High ESD rated value: 4KV HBM, 1KV CDM, 200V mm Board and Software

Application

Replace resistive gamma solutions

TFT-LCD reference driver

Dynamic gamma control

Instructions buf20820

is a programmableable The benchmark voltage generator is designed for gamma correction in the TFT-LCD panel. It provides 18 programmable output for gamma correction, two channels for VCOM adjustment, and the resolution of each channel is 10 bits. It provides a one -time programmable (OTP) memory, allowing users to store gamar voltage on the chip. This does not require external EEPROM.

This programmable replaced the traditional and time -consuming process of changing resistance to optimize various gamma voltages, and allows designers to quickly determine the correct gamma voltage of the panel. The required voltage changes can also be easily achieved without changing the hardware.

The BUF20820 uses TI's latest small geometric simulation CMOS process, which makes it a very competitive choice for comprehensive production, not just evaluation.

Each output is programmed through the two -line interface of industrial standards. Unlike the existing programmable buffer, the BUF20820 provides a high -speed mode that allows the clock speed to be as high as 3.4MHz.

For lower or higher channels, please contactYour local sales or marketing representative.

BUF20820 offers PowerPad #63722; software packages in HTSSOP-38. The specified temperature range is 40 ° C to+85 ° C.

BUF20820 related products

Typical features

TA +25 ° C, vs 18V, vsd 5V, vREFH 17V , VREFL 1V, RL 1.5K ground, when CL 200pf, unless there is another instructions.

Application information

A programmable F2 -bit output and programmable reference voltage output, each channel can be adjusted by 18 -bit programming. It allows a very simple and efficient adjustment of gamma benchmark voltage and VCOM voltage. BUF20820 is programmed through high -speed standard dual -line interface. The BUF20820 provides a dual register structure for each DAC channel to simplify the implementation of dynamic gamma control. This design allows pre -load register data to quickly update all channels at the same time.

Cushioner 1 9 can swing within the 200mv range of the positive electrode power supply rail, and swing within the range of 0.6V of the negative electrode power supply track. The buffer 10-18 can swing to the 0.8V range of the positive power supply rail and the 200mv range of the negative electrode power supply rail.

BUF20820 can use 7V to 18V analog power supply voltage and 2V to 5.5V digital power supply. Digital power supply must be used or at the same time before or at the same time to avoid excessive current and power consumption; if you only connect to the simulation power supply for a long time, it may damage the passage of the equipment time. Figure 7 shows the regular requirements of power supply.

FIG. 8 shows the BUF20820 in typical configuration. In this configuration, the BUF20820 device address is 74h. Once the data is received in the corresponding register (LD 0), the output of each digital modular converter (DAC) is updated immediately. For the maximum dynamic range, set VREFH vs 0.2V, VREFL GND+0.2V.

Overview of the dual -line bus

BUF20820 communicates through industrial standard dual -line interfaces to receive data from the mode. This standard uses the two -line open -road leakage interface to support multiple devices on a single bus. The bus is only driven to low logic. The equipment that initiates communication is called the main device, and the device controlled by the main device is from the device. The host generates serial clock on the clock signal line (SCL), controls the bus access, and generates start and stop conditions.

In order to address specific devices, when the SCL is at high electricity, the host will passData signal (SDA) starts the startup condition from high logic levels to low -logo levels. All the machines on the bus are shifted from the address byte by bytes, and the last one said whether it is necessary to read the operation or write operations. During the ninth clock pulse, the sub -addressing machine responded to the host by generating a response and lowering the SDA.

Then start the data transmission, send 8 -bit data, and then send a confirmation bit. During the data transmission process, when the SCL is high, the SDA must be stable. When SCL is high, any change of SDA will be explained as startup or stop conditions.

Once all data is transmitted, the main device will generate a stop condition. When SCL is high, SDA is pulled from low to high.

BUF20820 can only be used as a device; therefore, it never drives SCL. SCL is just the input of BUF20820. Table 1 and 2 summarize the address and command code of the BUF20820, respectively.

The address of the BUF20820

The address of the buf20820 is 111010x, where X is the state of the A0 pin. When the A0 pin is low, the device will be confirmed on the address 74h (1110100). If the A0 pin is high, the device will be confirmed on the address 75h (1110101).

Other valid addresses can be implemented by simple mask changes. Please contact your TI representative to obtain information.

Data rate

The dual line bus runs at one of the three speed modes: Standard: Allow clock frequency as high as as high 100kHz; Quick: Allow clock frequency as high as 400kHz; and high -speed mode (or HS mode): allow clock frequency to reach 3.4MHz.

BUF20820 is completely compatible with all three modes. Under standards or fast mode, the use of equipment does not require special operations, but the high -speed mode must be activated. To activate the high -speed mode, send a special address byte 00001xxx after the start -up condition, SCL 400kHz; XXX is the only bit of the host of HS, which can be any value. This byte is called HS main code. (Please note that this is different from the normal address bytes, and the low position does not indicate the reading/writing status.) No matter what the last three digits are, the BUF20820 will respond to a high -speed command. The BUF20820 will not confirm this byte; the communication protocol is prohibited to confirm the HS main code. After receiving the main code, the BUF20820 will open its HS mode filter and communicate at a frequency of up to 3.4MHz. By generating uninterrupted repetitions, you can start additional high -speed transmission without sending HS mode bytes. BUF20820 will exit the HS mode under the next stop condition.

General call reset and power power

[12]3] The BUF20820 response is generally called and reset, that is, the address byte 00h (00000000 0000), and then the data byte 06h (0000 0110). BUF20820 confirms these two bytes. After receiving the general call reset, the BUF20820 executes completely internal resetting, as if it has been turned off and then turned on. It always confirms the general call address bytes of 00H (0000 0000), but it is not confirmed that any general call data bytes other than 06H (0000 0110) are not confirmed.

BUF20820 automatically executes reset after power generation. As a part of reset, the BUF20820 configuration is changed to all outputs to the programmatic OTP memory value, or (VREFH VREFL)/2 (if the OTP value is not yet programmed).

When sending the device address, the BUF20820 resets all outputs to OTP memory (or (VREFH VREFL)/2, if the OTP value is not programmed), and then send an effective DAC address, D7, D7 Set up to ""100"" to D5. If these bits are set to ""010"