2 Fuck

Synchronous rectification control

Super fast load response

Integrated large current door

Driver: up to 2A grid pole current [123 ]

TTL is compatible with 5 -bit programming

output voltage from 0.800V to 1.550V

25mv stepping

dynamic video management

0.6% Output voltage accuracy

10%contribution accuracy

Digital 2048 step Step Soft start

Overvoltage protection

Realized current protection

[

123] Using MOSFET's RDSON or A

sensor

External adjustable oscillating device

Internal fixed at 200kHz

The power output and good output and good output and good power output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and good output and output and good output and output and good output and output and good output and output and good output and output and output and output and output and good power output and output and output and output and output and good power output and output and output and output and output and good power output and output and output and output and output and output and good power output and output and output and output of the power Inhibitory

Function

Remote control buffer

Packaging: SO-28

Application

Server and workstation

Large current power supply

Micro processor

distributed power supply

Instructions

This device is a power controller design for providing high -performance DC/ DC large current microprocessor conversion. This device implements a double -phase antihypertensive controller with a phase shift phase of 180 ° between each phase. A accurate 5 -digit modular converter (DAC) allows adjusting the output voltage 0.800V to 1.550V, 25mv binary steps, and real -time management video code changes. High -precision internal benchmarks ensure that the selected output voltage should be within a range of ± 0.6%. This peak value door driver provides fast switching to the external power MOS switch loss that provides low power consumption. This device guarantees the rapid protection of the current and overload/under pressure of the load. Provide an internal crowbar, rotate MOSFET on the lower side, if the voltage is detected. In the case of passing, the system works in the constant current mode.

Electric characteristics

VCC u003d 12V ± 15%, TJ u003d 0 to 70 ° C, unless there are other regulations

]

Electrical features (continued)

VCC u003d 12V ± 15%, TJ u003d 0 to 70 ° C, unless there are other regulations

[ 123] Device description

This device is an integrated circuit implemented by BCD technology. It provides complete control logic and protectionA high-performance bilateral drop-down DC-DC converter suitable for microprocessor power supply. Design a two -phase synchronous rectification buck topology drive N -channel MOSFET. 180 degrees transposition is provided between the two phases, allowing reducing the input capacitor current ripples while reducing the size and loss. The output voltage of the converter can be accurately adjusted. Through programming VID pins, from 0.825V to 1.575V, 25 MV binary steps, the maximum tolerance of temperature and wire voltage changes is ± 0.6%. This device automatically adjusts the hammer digital modulus converter above 25 millivoli to avoid using any external settings. The dynamic video code of the device changes, and the video table after step to the new configuration does not require external components. The device provides average current mode control and fast transient response. It includes a 150kHz self -exciting oscillator. The error amplifier has a converting rate of 15V/μs, allowing high converters to fast transient performance bandwidth. The current information is in a full differential mode through lower MOSFETS RDSON or transgender resistors. Current information correction PWM output to balance the average current of each phase. The current sharing between the two phases is then limited to ± 10%static and dynamic conditions. This device can prevent over current, and each phase has an OC threshold to enter the constant current mode. Because the current is read through the low -side MOSFET, the constant current makes the bottom current of the inductors be a triangular waveform. When detection is detected, the device locks and the fault pins drive high. The device also performs overvoltage protection. The protection may immediately disable the device to open the lower drive and drive a high fault pins.

oscillator

The internal fixation of the switching frequency is fixed at 150kHz. The switch frequency produced by the oscillator at a fixed frequency of the oscillator will double the switching frequency generated on the load side. The internal oscillator produces a triangular waveform and is used to charge and discharge the internal capacitors at a constant current. The current transmitted to an oscillator is usually 25A (FSW u003d 150kHz), and it can change the external resistor (ROSC) connected to the external resistor (ROSC) connected to the OSC pin and GND or VCC. Because when the OSC pin is maintained at a fixed voltage (typical. 1.237V), the frequency of the frequency (internal gain is 6kHz/μA) depression (mandatory) current proportional change. Especially when connecting it to GND, the frequency will increase (the current sinks from the pins), and the ROSC is connected to the VCC u003d 12V at the same time. According to the following relationship, the frequency is reduced (the current is forced to enter the pins):

] Please note that the 25μA current is pressed into the foot, and the device will stop switching because there is no current to the oscillator.

digital mode converter

The built -in digital mode converter allows the output voltage from 0.800V to 1.550V25mV, as shown in the previous table 1. The internal benchmark is adjusted to ensure the accuracy of the output voltage ± 0.6%, zero temperatureThe coefficient is about 70 ° C. The adjustment internal reference voltage is programmed by voltage recognition (VID) pin. These are the internal DAC TTL compatible inputs to provide a series of resistors to provide internal voltage benchmark partitions. VID code drives a multi -way relicant, which selects a voltage at the precise point of the pressure division. The DAC output is transmitted to the amplifier that obtains the Vprog reference voltage (that is, the setting value of the error amplifier). Internal pull -down is provided (achieved with a 5 μA current generator, the highest 3.0V typical value); in this way, the programming logic ""1"" is enough to keep the pin floating, and the programming logic ""0"" is enough to make the pin short short. Put to GND. Programming ""11111"" code, device enters NOCPU mode: All MOSFETs are closed to protect failure. Conditions have been locked. Voltage recognition (VID) pin configuration also sets good power threshold (PGOOD) and/OVP/UVP threshold.

Dynamic video conversion

This device can manage dynamic video code changes, allowing the output voltage during normal device operation. The device checks the VID code modification of each clock cycle (synchronized with PWM slope). Once the new code remains stable during a clock cycle, the quotation will gradually increase or decrease by 25mV per clock cycle until it reaches the new VID code. During the conversion process, the VID code will be ignored; after the conversion is completed, the device restarts the surveillance of VID. Okay, the signal is blocked during the conversion process. When OVP/UVP is still in active, the signal is re -activated after the conversion is completed.

The integrated large current drive allows using different types of power MOS (you can also use multiple MOS to reduce fast switching and conversion. Power supply, PHASEX pins are used for returning. The driver's low -voltage side MOSFET uses VCCDRV pin to supply power, PGND pins are used for circuit. At least 4.6V voltage at VC CDRV pins can start the operation of the device. This controller. Including a complex anti -breakdown system, to minimize the transmission time of the low -side diode to maintain good efficiency and save the use of the Schottky diodes. Open: When the high side MOSFET is closed, the voltage on the source starts to decrease; when the voltage reaches 2V, the low -side MOSFET gate driver is delayed.到1V以下，高侧mosfet栅极驱动采用延迟30ns。如果电感为负，高边mosfet的源永远不会下降。

即使在这种情况下，为了允许低侧mosfet的开启， A watchdog controller is enabled: if the source high side MOThe drop of SFET does not exceed 240ns, and the low side MOSFET is opened, which allows the negative current of the inductor to recycling. This mechanism allows system adjustment, even if the current does not. Bootx and VCCDR pins and IC power (VCC pins) and signal grounding (SGND) and power supply ground (PGND pins) to maximize the increase of switching resistance. For different drivers, the selection of MOSFET has given high flexibility to allow MOSFETs with logical levels. You can choose several supply portfolios to optimize the performance and efficiency of the application. Flexible power conversion; 5V or 12V bus can be selected freely. Figure 3 shows the peak current of the upper drive and the lower drive of the two phase. 10NF capacity load has been used. For the upper-layer drive, the source current is 1.9A, and the absorption current is 1.5AVBOOT-V phase u003d 12V; similarly, for the lower driver, the source current is 2.4A, and the trap current is 2AVCCDR u003d 12 volts.

current reading and overcurrent

Via a low -voltage side MOSFET RDSON or through an inductive resistor (RSENSE) and convert to a current internally. The transmission conductors are placed outside the chip through the external resistance RG, and the IsenX and PGNDSX pins that are read towards the reading point are placed. The readings of the full differential current can inhibit noise and allow the sensor element to be placed in different positions without affecting the measurement accuracy. The current reading circuit is on the low side MOSFET. During this period of time, the response to keep the needle isenx and PGNDSX under the same voltage. When the reading circuit is closed, the internal clamp keeps the two pins under the same voltage from the IsenX pin sinking the necessary current (if if you If the IsenX pins (if you If the IsenX pins (if you If the IsenX pins (if you if the IsenX pins (if you If the IsenX pins (if you, the current (if you If the IsenX pins (if you If the IsenX pins (if you, the current (if you If the IsenX pins (if you, The low side MOSFET RDSON needs to execute the Sense to avoid overcoming the absolute maximum rated value on the IsenX pin). The patented current reading circuit allows very accurate and high bandwidth reading, whether it is the positive electrode or negative current. The circuit tracks the current of the sensing element at a high speed to keep the transmission of the conductors. In particular, the current reading current it reads in the second half of the closure due to the opening of the MOSFET, which reduces the time of noise injection into the device (see Figure 4). The tracking time must be at least 200 nan seconds. To correctly read the conveying current, the circuit provides a constant 50μA current from the PGNDSX pin, and keeps the pins and PGNDSX in the same voltage. Reference Figure 4, the current in the Isenx pin is given the formula from the following formula:

Among them RDS, ON's low -end MOSFET and RG are the resistors that read the number of readings between the cross -guided IsenX and PGNDSX pins; iPhose is the current aspect of the current carried by each pin, especially in the middle of the oscillator cycle.The current information of the internal reproduction of the current is expressed as follows:

Because the current is read in the differential mode, the negative current information is also It will be retained; this allows the device to check whether there is a dangerous return between the two phases to ensure the current. From the current information of each phase, obtain the information about the total current (IFB u003d IInfo1+Iinfo2), and take the average current of each phase (IAVG u003d (IInfo1+Iinfo2)/2). Then, iinfox is compared with IAVG to correct the PWM output to balance the current carried by the two phases. Cross -conductor RG can be designed as a current information of 25 μA per phase of the rated load; the over -current intervention threshold is set to 140%of the nominal value (iinfox u003d 35 μA). According to the above relationship, the over -current threshold (IOCPX) of each phase must be set to half in the maximum current current, result:

Because the device can sense the output current of the low side MOSFET ( Or the device connected in series) The device limits the bottom of the electrical current triangular waveform: the current that the current when the current when the current flows into the detection element is greater than the IOCPX (IInfox u0026 GT; 35μA). Now the relationship between the maximum guide time and current (where T is the switch cycle T u003d 1/FSW):

This linear relationship is 0.80 · t when the load is zero load. In two different behaviors of the device when the maximum current is 0.40 · T:

1.T limits output voltage.

When the current of each phase reaches the maximum connection time, this is the case u0026 lt; 35μA). Figure 5A shows that the maximum output voltage that the device can adjust can be imposed by the previous relationship. If the expected output characteristics exceed the maximum output overput overput overput, the output voltage generated will decrease. In this case, the device does not perform constant current restrictions, but only limits the maximum connection time after the previous relationship. Before the UVP or IFB u003d 70 μA is detected, the output voltage follows the characteristics generated (as shown in Figure 5b).

2. Constant running

When the current of each phase reaches the IoCPX (IInfox u0026 GT; 35μA) Happening. The device enters the quasi -constant current operation: The low -side MOSFET keeps opening the clock cycle below IOCPX (IInfox u0026 LT; 35μA) before the current reading. The high -sided MOSFET can be used in the next available clock cycle. A ton appropriately applied by the control loop, the device works in a usual way until another OCP event is detected. This means that in the case of overcurrent, due to currentThe fluctuations increase, and the average current will increase slightly. In fact, the increase in connection time is due to the increase of the off -cutting time, because the current must reach the bottom of the IOCPX. The worst case is when the connection time reaches the maximum value. When this happens, the device works in the constant current, and the output voltage decreases as the load increases. More than the UVP threshold will cause the device to lock (the fault pins are driven by high level). Figure 6 shows that this working condition can observe the peak current (IPEAK) greater than IOCPX, but it can be determined as follows:

Among them, VOUTmin is the minimum output voltage (VID-30% ,As follows). The device works in a constant current, and the output voltage decreases as the load increases until the output voltage reaches the voltage threshold (Voutmin). When this threshold is exceeded, when all MOSFETs are turned off, the fault pins are driven by high levels, and the device stops working. The circulating power supply is restarted. The maximum current current result of this constant flow is:

In this special case, the result of the switching frequency is reduced. The longest time (Tonmax) closure time is on time depends on the application:

When the Iinfox reaches 35 μA (if B u003d 70 μA), the current is still set. Full load value is just the convenience value of IFB. Because the OCP intervention threshold is fixed, in order to modify the percentage of the load value, it can be simply believed that, for example, when it has 170%on the OCP threshold, it is equivalent to infox u003d 35μA (if B u003d 70 μA). The full -load current will be with iinfox u003d 20.6μA (if B u003d 41.1 μA).

Integrated drooping function

This device uses a drooping function to meet the requirements of high -performance microprocessors, reducing the size and cost of power output capacitors. This method ""restores"" the part of the voltage drop caused by the output capacitance ESR in the load transient, which introduces the dependency of the output voltage and the load current. As shown in Figure 7, the ESR drops in any case, but the use drop is reduced, but the use drop is reduced, but the use drop is reduced, but the use drop is reduced, but the use drop is reduced, but the use drop is reduced, but the use drop is reduced. The speed function is the smallest output voltage. In fact, the speed reduction function introduces a static error that is proportional to the output current (VDROOP in Figure 8). Because the device has the average current mode adjustment, the total current provided is used to achieve a speed reduction function. This current (equal to the sum of two iinfox) comes from FB pins. Connect a resistor and VOUT between this pin, and the total current information is only flowing in this resistance, because compensation networks always connect a capacitor in series (see Figure 8). The adjustment voltage is equal to:

Since IFB depends on the current information of the two -phase, the relationship between the output characteristics and the load current is:

]

Under the rated full load (IFB u003d Iinfo1+Iinfo2), the feedback current is equal to 50 μA and OC intervention, the feedback current is equal to 70 μA threshold, so the maximum output voltage deviation is equal to: u0026#8710; v full positive load u003d -rfb · 50 μA u0026#8710; voc_ intervention u003d -rfb · 70μA

The speed reduction function is only provided on the positive load; if the negative load is applied, then infox u0026 lt; No current sinks from FB. The device is adjusted under the voltage of VID programming.

Remote voltage detection

This device integrates a remote sensor buffer, so that the realization of the remote sensor of the output voltage does not require any other external components. In this way, the programming output voltage is adjusted between the remote buffer input. If the device is used for VRM, the motherboard tracking loss or the connector loss module will be compensated. Extremely low offset amplifier is used to regulate voltage detection by pins FBR and FBG (FBR) remote sensing output voltage, while FBG is used for ground detection) and reports the unified gain pins of the voltage internally in the vSEN. Keeping the FBR and FBG trajectory parallel and the plane of the power supply will cause any co -mode coupling to pick up noise. If you do not need to be remote, it is enough to connect the RFB directly to the adjustment voltage: VSEN becomes unconnected, and the output voltage is still induced by remote buffer. In this case, the FBG and FBR pins must be connected to the specified voltage (see Figure 10). The remote buffer includes in a fine -tuning chain so that the accuracy of ± 0.5%on the output voltage is used: eliminating it from the control loop from the control circuit will cause RB to increase the adjustment error offset the deterioration of the equipment.

output voltage monitor and protection

This device monitors the regulating voltage through Pin-VSEN to establish a good signal and manage OVP/UVP to manage OVP/UVP condition. If the voltage that VSEN senses is not within the range of ± 12%(typical values) of the programming value, the power output is forced to be compulsory to low -value values. It is an output of a drain, and it is only enabled after the soft start (2048 clock cycle). During the soft start, the pin was forced to be low. Provide under pressure protection. If the output voltage monitored by VSEN is lower than 60%of the reference voltage during a clock cycle, the device will turn off all MOSFETs and drive OSC/fault high (5V). Conditions have been locked, and recovery needs to be recovered. Overvoltage protection is also provided: When VSEN monitored the voltage of the OVP threshold, the VOVP controller permanently opens the low side MOSFET, and at the same time, the high side is turned off to protect the load. OSC/fault pins driver is high level (5V), power supply (VCC) shutdown and on are necessary to restart the operation. Overvoltage percentageVID compilation is set up by the ratio of a fixed OVP threshold VOVP and reference voltage:

Overvoltage and under voltage are also activated during soft start (below the output voltage 0.6 After V). In this case, the reference value used to determine the ultraviolet threshold is the increase of the increase in the 2048 soft startup digital counter, and the reference for the OV threshold is the final reference to be programmed by the VID pin.

Soft start and inhibitory

When starting, a slope is generated, and the final value of the circuit reference from 0V to VID in programming is 2048 clock cycle, as shown in Figure 10. Once the softening starts, the reference value increases: the upper and lower MOS start to switch, and the output voltage begins to increase with the closed loop adjustment. After the digital soft start is completed, the power comparison is enabled, and then the PGOOD signal is driven by high levels (see Figure 10). When the pressure comparator is enabled, when the reference voltage reaches 0.6V, if the VCC and VCCDR pins will not exceed their own startup threshold. During the normal operation period, if any underwriting voltage is detected on one of the two power supply, the device is closed. The voltage of forced OSC/Inh pins is lower than 0.6V (typical values). Device will be disabled: all power MOSFETs and protection shutdown until the conditions are eliminated.

Input a capacitor

The design of the input capacitor mainly considers the input average cubic current, and the input average root current depends on the duty occupation. For example 11 shown in Figure 11 Essence Considering the dual -outbound structure, the input uniformly running current runs lower.

You can observe the situation where the input average root value is the worst is the most equal -phase equivalent input current. When d u003d 0.25 and d u003d 0.75 occur. The power consumption of input capacitance is equal to:

The design of the input capacitor is to maintain the ripple that is relative to the maximum load occupation ratio. The high RMS value required to reach the CPU power application can also be achieved by more than one physical capacitance. The equivalent square -meter root current is the average square current current of a single capacitor. The input of large -capacity capacitors must be evenly distributed between high -side drain MOSFETs, and as close as possible during the load transient process, first reduce the switching noise. Ceramic capacitors can also bring noise to the noise of the frequency of efficient benefits, and the noise generated by the parasitic element along the power path.