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2022-09-19 17:33:03
ADN4690E/ADN4692E/ADN4694E/Adn4695E is 3.3 V, 100 Mbps, half dual-workers and full duplex, high-speed M-LVDS transceiver device
Features
Multi -point LVDS transceiver (low -voltage differential signal driver and receiver pair)
[123 ] Switching rate: 100 Mbps (50 MHz)
Support bus load: 30Ω to 55Ω
The choice of two types of receiver types -Gype 1 (
ADN4690E/ ADN4692E ): Laingling 25 mv -Type 2 (
Adn4694e/ ADN4695E ): Threshold to shift 100 mv
for the protection of the idle fault protection of the road and bus[ [
[[ [ [
[123] meets TIA/EIA-899 M-LVDS standards
M-LVDS bus failure up/lower electricity
]
The controlled conversion time of the drive output of the drive
Noise Communication
Disable or power-off Drive output high -Z
enhancement of the bus pins ESD ESD Protection
± 15KV HBM (human model), air discharge
± 8kv HBM (human model), contact discharge ± 10 kV IEC 61000-4-2, Air discharge
± 8KV IEC 61000-4-2, contact discharge
Work temperature range: -40 ° C to+85 ° C [123 123 ]
Provide 8-line (ADN4690E/ADN4694E) and 14 lines (ADN4692E/ADN4695E) soIC packaging
-The backplate and cables and cables Multi-point data transmission
-D multi-clock distribution
-The low power consumption, high speed, can replace the short RS-485 link
-The basis Facility
General description
ADN4690E/Adn4692e/Adn4694e/Adn4695E is a multi-point, low-voltage differential signal (M-LVDS) transceiver (drive and receiver pair), and the working speed can reach 100 Mbps (50 MHz). Realize the rotation rate control at the drive output terminal. The receiver detection bus status, within the co-mode voltage range of -1 V to +3.4 V, the differential input is only 50 MV. ESD protection with up to ± 15 kV on the bus pin. These components follow the TIA/EIA-899 standard of M-LVDS and supplement the TIA/EIA-644 LVDS device with additional multi-point functions.
ADN4690E/ADN4692E is a type 1 receiver with 25 MV lag, so slow changes or input losses will not cause output oscillation. ADN4694E/ADN4695E is a type 2 receiver that displays the offset threshold to ensure the output status of the bus (busy fault protection in the bus) or input road (open road failure).
These parts provide half -dual -workers (ADN4692E/ADN4695E) in the 8 -drawing SOIC packaging in the 8 -lead SOIC package. The selection of ADN469XE components is shown in Table 1. 
Typical performance features 
The test circuit And switch feature
Drive voltage and current measurement
Driver timing measurement
Receive Measurement
Operation theory
ADN4690E/Adn4692e/ADN4694E/ADN4695E is used for high -speed (data rates up to 100 Mbps) sending and receiving multiple points, multiple points, and multiple points, and more points, multiple points, multiple points, and multiple points. The transceiver of low-voltage differential signal (M-LVD). Each device has a differential line drive and a differential line receiver, allowing each device to send and receive data.
Multi -point LVDS expands the existing LVDS low -voltage differential signaling method, allowing two or more nodes to communicate. A maximum of 32 nodes can be connected on the M-LVDS bus.
Half dual -work/full dual -work operation
Half dual -work operation allows transceiver to send or receive, but cannot be sent and received at the same time. However, through full -duplex operations, the transceiver can be sent and received at the same time. ADN4690E/ADN4694E is a semi -dual -worker equipment, where the driver and receiver shared the difference in bus terminals. Adn4692e/aDN4695E is a full -duplex equipment with a special drive output and receiver input pins. Figures 36 and Figure 37 show the typical half-dual-work and full duplex bus topology of M-LVD, respectively.
Three -state bus connection
By disabling a drive or receiver, the output of the device can be placed in a high impedance state. This allows multiple drive output to connect to a single M-LVDS bus. Note that on each bus, only one driver can be enabled at a time, but multiple receivers can be enabled at the same time.
You can use the driver to enable the pins (de) to enable or disable the driver. When it is high, the DE enables the drive output; when it is low, the DE outputs the drive to a high impedance state. Similarly, a source low receiver enables the pins (RE) to control the receiver. The pin is set to a low -enabled receiver, and it is set to the high impedance state to the high impedance state.
The authentic values of the drive and receiver output state under various conditions are shown in Table 10, Table 11, Table 12, and Table 13.
True value table
Half -dual -working drive (Adn4690e/ADN4694E)
In order to minimize the interruption of the bus when adding a node, the device is called or electric During the power off, the M-LVDS output of the device remains without failure. This function allows the device to insert the device into the real-time M-LVDS bus, because the bus output was not opened before the device was fully powered. In addition, when the device is powered off, all outputs are in a high impedance state.
Failure conditions
ADN4690E/ADN4692E/ADN4694E/ADN4695E contains short -circuit current protection. In the case of short circuit in the bus, protecting parts under the fault conditions. This protection restricts the current at the output end of the faulty condition to 24 mAh to prevent short-circuit faults between -1 V and +3.4 V. Any network failure must be removed to avoid data transmission errors and ensure the reliable operation of the data network and any device connected to the network.
The receiver input threshold/failure security
There are two types of receiver types to choose from, both types include short -circuit protection.
ADN4690E/ADN4692E 1 receiver contains 25 MVHurry up. This ensures that slowly changing signals or input loss will not cause oscillation of the receiver output. Type 1 receiver threshold is ± 50 mv; therefore, if the difference between A and B is about 0 V, the state of the receiver output is uncertain. If the bus (A and B are about 0 V), and the driver is not enabled on the connection node, this state will appear.
Type 2 receiver (ADN4694E/ADN4695E) has the open road and bus idle fault protection. The input threshold offset 100 mV so that when the bus or the receiver is input open, the logic of the receiver output is low.
The threshold of different receivers of the two receivers type is shown in Figure 35. See Table 12 and 13 under the output status of the receiving machine under various conditions.
M-LVDS expands the low power and high-speed differential signaling of LVDS (low-voltage differential signal) to the bus topology network on the bus topology network The multi -point system of multiple nodes is connected to the short distance.
In M-LVDS, send nodes to drive the differential signal by transmitting medium (such as twisted pair). The sending signal sent to detect the differential voltage along other receiving nodes connected along the bus, and then the differential voltage can be converted back to the single -end logic signal by the receiver.
The communication line is usually connected by the resistor (RT) at both ends, and its value is selected to match the characteristic impedance of the matching medium (usually 100Ω).
For a half -dual -worker multi -point application (as shown in Figure 36), only one driver can be enabled at any time. The full -double node allows the main topology, as shown in Figure 37. In this configuration, the master node can send and receive data from the node at the same time. At any time, only one from the node can enable its driver to transmit the data back to the main node.
[1] gives v 3.3 All typical values in V and T 25 ° C.
[2] The jitter parameters are guaranteed by design and characteristics. The value does not include stimulus jitter.
[3] t t 0.5 nan seconds (10%to 90%), and more than 30,000 samples were measured.
[4] The jitter specification of the peaks includes the jitter caused by pulse bias (t).
[5] t t 0.5ns (10%-90%), measured on 100,000 samples.
[6] HP4194A impedance analyzer or equivalent instrument.
[7] Not applicable.
[8] Z parts that conform to ROHS.