5 Input Power Stage Space-Based Information Platform - TLE 7240SL is an octal low-side relay switch. The power stage is built with N-channel vertical power MOSFET transistors. 5.1 Power Spider - The TLE 7240SL is supplied by two power lines VDD and VDDA. The digital power line VDD is designed to be functional over a wide voltage range. The analog power supply VDDA supports 5 V power supply. There is a power-on reset function implemented on two power supply lines. After power-up, all SPI registers are reset to their default values and the device is in standby mode. Capacitor pins VDD-GND and VDDA-GND are recommended. There is a reset pin available. A low level on this pin causes all registers to be set to their default values and quiescent supply current to be minimized. 5.1.1 Limp-home mode SPIG-TLE 7240SL provides the system with the capability of fail-safe operation in the final drive-only channel. This limp home mode is activated by a high signal on pin LHI. In this mode, the SPI registers are reset and the input pins are routed directly to their corresponding channels OUT1 to OUT4, see Table 2 for details. OUT5 to OUT8 are turned off in limp home mode. Also, SPI will be ignored and all input pins are referred to as VDDA in order to ensure the specified mode of operation if the digital power supply or microcontroller fails. RST reset signal overlaid on Langham Hospitality Group's high signal. If the limping home is on standby the device will therefore wake up and enter the limping home mode. After a limp home job resets all registers, the device enters standby mode with a low logic RST state, or returns to idle (all channels off). will get the TER flag on the next SPI transfer