-
2022-09-15 14:32:14
OPA656 is a broadband, stable unit gain, field -effect transistor input computing amplifier
Features
● 500MHz unit gain bandwidth
● Low input bias current: 2Pa
● Low offset and drift: ± 0.25mv, ± 2 μV/° C
●低失真：在5MHz时为74dB SFDR
●高输出电流：70mA
●低输入电压噪声：7nV/√Hz
[123 ] Application● Broadband photoelectric diode amplifier
● Sample keeping buffer
● CCD output buffer
● ADC input buffer
[[123] ● Broadband precision amplifier
● Measurement and test
Description
OPA656 combined with a very broadband belt, unified gain stable, voltage feedback computing amplifier and FET input level, for the input level ADC (Model Converter) buffer and transient applications provide an ultra -high dynamic range amplifier. Very low DC errors have good accuracy in optical applications.
High -unit gain stable bandwidth and JFET input allows outstanding performance in high -speed low noise points.
High input impedance and low bias currents are supported by FET input from ultra -low 7nv/√Hz input voltage noise support to realize very low integrated noise in the transients of broadband photoelectric diode.
In view of the high 230MHz gain bandwidth product of OPA656, it can achieve a wide transient bandwidth. As shown in the figure below, even if the 47pf source capacitor is 1M transient gain, it also provides a 1MHz A -3DB bandwidth.
Related operational amplifier products
Typical features: vs u003d ± 5V 
Application information 
] Broadband and dizzy operation
OPA656 provides a unique combination broadband, uniform gain stability, and the VC -pruning JFET input phase of the DC accuracy of the voltage feedback amplifier. Its 230MHz high -gain bandwidth (GBP) can be used to provide high -signal bandwidth for low -gain buffer, or provide broadband and low -noise transient bandwidth to the optoelectronics diode detector application. In order to achieve the entire performance of OPA656, you need to pay close attention to the printing circuit board (PCB) Layout and component selection, as described in the rest of the data table.
FIG. 1 shows the non -invasive gain of the +2 circuit, which is used as the basis for most typical characteristics. Most curves use a signal source of 50 driving impedance, and the measurement device displays 50 load impedance. In Figure 1, 50 parallel resistors at the VI terminal are matched with the source impedance of the generator, while the VO terminals at 50 series resistors provide matching resistors for the measuring device load. Generally, the voltage swing specification of the data table is located in the output pin (VO in Figure 1), and the output power specifications are under the load of 50 The total 100 load with 500 the total feedback network load is combined, indicating that the OPA656 effective output load in Figure 1 circuit is 83
The voltage feedback amplifier is different from the current feedback product. It can use a wide range of resistance to set its gain. In order to keep the control frequency of the African vertical voltage strokes in Figure 1, the parallel combination of RF | RG should always lt; 200 . In non -vertical configuration, the parallel combination of RF | RG will form the pole with parasitic input capacitors at the reverse node (including layout parasites) of the OPA656. In order to obtain the best performance, the frequency of the pole should be greater than the closed bandwidth of OPA656. Therefore, for the unit gain follower application, it is recommended to directly enter the short circuit from the output to the reverse input.
Broadband and reverse gain operations
The circuit in FIG. 2 shows the inverter gain for most of the typical characteristics of the inverter. In this case, the input impedance is used to use the additional resistor RM to achieve the 50 In the circuit board environment, in the circuit board environment, at the output of the previous level, OPA656 is used as a inverter amplifier. The input impedance matching is optional.
In this configuration, the output treats the feedback resistor as the additional load parallel to the 100 In the case of restricting RF | rg lt; 200 parallel combination, increasing the radio frequency value to reduce the output load (improving the harmonic distortion) is usually useful. For the inverted gain with higher DC accuracy provided by FET input OPA656, consider the higher gain bandwidth multiplication OPA157.
FIG. 2 also shows non -vertical input connected to the ground. Generally, the bias current to the ground resistance to eliminate the DC error caused by the input bias current effect. This is only useful when the input bias current matchs. For JFET parts like OPA656, the input bias current does not match, but it is low to ( lt; 5Pa) start, so DC errors caused by input bias currents can be ignored. Therefore, for the condition of the inverter signal path, it is not recommended to use the resistor at the non -rotating input.
Broadband, high sensitivity, transient design
The high GBP low input voltage and current noise of OPA656 make it an ideal broadband transient amplifier with low to moderate transient gain. The higher transient gain ( gt; 100k ) will benefit from the low input noise current of FET input computing amplifiers such as OPA656. The homepage of the data table shows an example of a transient design. Large -scale detectors need high bandwidth design to benefit from the low input voltage noise of OPA656. This input voltage noise diode source capacitance makes it peak the frequency. In many cases, it can become a limited factor for input sensitivity. The key element of design is the expected diode capacitor (CD) of reverse bias voltage (—VB), the required transient gain, and GBP of RF and OPA656 (230MHz). Figure 3 shows a design from the 25K transient gain. In the case of setting these three variables (including adding the parasitic input capacitor of OPA656 to CD), the feedback capacitance (CF) can be set to control the frequency response.
In order to obtain the largest flat second -order Bartvos frequency response, the feedback pole should be set to:
will be will will be will will be the next The co -mode and differential mode input capacitance (0.7+2.8) PF is added to the 25PF diode source capacitance in FIG. 3 and use the 230MHz GBP of OPA156 to aim at 50K the transient gain needs to set the feedback pole to 3.8MHz. This will require a total feedback capacitor to 0.8pf. The parasitic capacitor of a typical surface installation resistor is 0.2PF, leaving the 0.6PF value required in Figure 3 to obtain the required feedback pole. 
The example of FIG. 3 will give about 5.7MHz using 0.6pf feedback compensation compensation compensation compensation compensation compensation. Flat bandwidth. 
[
[
[ 123]In the formula:
IEQ u003d Output noise bandwidth limit is F LT; 1/(2πrfcd) input noise current.
in u003d Input current noise of the input input input input.
EN u003d Input voltage noise of the operation amplifier.
CD u003d diode capacitors.
F u003d Frequent band restrictions frequency, with Hertz as a unit (usually filtering before further signal processing).
4KT u003d 290 ° K is 1.6E – 20J.
For Figure 3 circuit, this expression is calculated to 3.8MHz feedback pole frequency, and the equivalent input noise current of 2.7Pa/Hz is given. This is much higher than 1.3FA/Hzor, just the operational amplifier itself. The result is mainly dominated by the last item in the equivalent input noise current expression. In this case, it is necessary to use a low -pressure noise computing amplifier.
Design tool
Demonstration device
Two print circuit boards (PCBS) can be used to use OPA656 to assist preliminary assessment circuit performance in its two packaging options. Both products are provided for free, as unpopular polychlorine benzene, and delivered with user guidelines. The abstract information of these fixed devices is shown in Table I.
Demonstration device can apply on the Texas instrument website () through the OPA656 product folder.
Operation recommendations
Set the resistor value to minimize noise
OPA656 provides very low input noise voltage, and also requires a low 14mA static power supply current. In order to make full use of this low input noise, you need to pay close attention to other possible noise factors. Figure 4 shows the noise analysis model containing all noise items. In this model, all noise items are considered noise voltage or current density items of NV/Hz or PA/Hz.
The total value of the output point noise voltage can be calculated as the square root of the output noise voltage. This calculation adds all the noise power of the output through a superposition method, and then takes the square root to restore the point noise voltage. Formula 1 shows the general form of the output noise voltage used in Figure 4.
This expression will be removed by the noise gain (GN u003d 1+RF/RG), which will give the equivalent input point noise voltage at the equivalent input point of the non -vertical input, such as formulas, such as formulas 2 shown.
Putting high resistance values u200bu200bin formula 2 can quickly control the total effect input noise. The source impedance on the non -rotating input 3K the addition of a Johnson voltage noise item, which is equivalent to the voltage noise item (7nv/Hz) of the amplifier itself. Although the JFET input of OPA656 is an ideal choice for high -source impedance applications, the overall bandwidth and noise will be limited by higher source impedance in Figure 1 in Figure 1.
Frequency response control
VoltageThe feedback computing amplifier, such as OPA656, shows that the signal bandwidth decreases with the increase in signal gain. Theoretically, this relationship is described by GBP shown in electrical characteristics. Ideally, the GBP except for non -rotating signal gain (also known as noise gain, or NG) will predict a closed -loop bandwidth. In fact, this is only established only when the phase margin is close to 90 °, just like in a high -gain configuration. At low gain (increase feedback factor), most high -speed amplifiers will show more complicated responses and low phase margin. Compensation OPA156 is given the largest flat -level Bartworth closed -loop response at a non -rotating gain of +2 (Figure 1). This has led to a typical +2 bandwidth 200MHz gain, far exceeding the prediction of 230MHz GBP except 2. Increasing gain will lead to the closer of phase margin, and the bandwidth will be closer to (GBP/NG) prediction values. At the gain of +10, OPA656 will show the use of a simple formula predicted 23MHz bandwidth and a typical GBP of 230MHz.
The unit gain stable calculation amplifier. For example, OPA656 can also use a capacitor to limit the feedback resistor. For non -vertical configurations in Figure 1, the gain will be reduced by reducing the frequency to the +1 capacitance by the feedback resistor. For example, in order to limit the gain of +2 design to 20MHz, 32PF capacitors can be parallel with 250 feedback resistors. However, this will only reduce gain from 2 to 1. In the reversal configuration in Figure 2, the feedback capacitance is used to limit the signal bandwidth. Add the same capacitors to the feedback in Figure 2 to set a pole in a 20MHz signal frequency response, but in this case, it will continue to attenuate the signal gain below 1. However, the output noise contribution caused by the input voltage noise of OPA656 will still only reduce the gain of 1 as the feedback capacitor is added.
Drive capacitance load
Capacitor load is one of the most harsh but most common load conditions for operators. Generally, the capacitor load is the input of ADC, including an additional external capacitance that can be used to improve the linearity of ADC. High -speed high -speed open ring gain blew, such as OPA656, when the capacitor load is placed directly on the output pin, it is easily affected by the decrease in stability and the peak of closed -loop response. When considering the opening resistance of the amplifier, this capacitance load introduces an additional pole in the signal path to reduce phase margin. Some external solutions are raised for this issue. When the main considering frequency response flat, pulse response and/or distortion, the simplest and most effective solution is to insert a series isolation resistor between the amplifier output and the capacitor load, and isolate the capacitor load and the feedback circuit. This will not eliminate the pole in the ring response, but shift it and add zero at a higher frequency. The effect of adding zero to eliminating the stagnation of the load polarity of the capacitor, thereby improving phase margin and improving stability.
Typical features show the recommended RS and capacitor load and the load frequency response generated by this. In this case, the design goals of the maximum flat frequency response are used. If you can tolerate certain peaks, you can use a lower RS u200bu200bvalue. In addition, when running at a higher gain (+2 in the typical features), a lower RS u200bu200bvalue is required for the minimum peak frequency response. Parasitic capacitor load is greater than 2PF, which can start to reduce the performance of OPA656. The connection of long PC board tracking, non -matching cables and multiple devices can easily lead to exceeding this value. Always consider this effect carefully, and add the recommended series resistors to the OPA656 output pin (see the plate layout part).
Disted performance
OPA656 can transmit low distortion signals in a high -frequency manner within a wide range of gain. The distortion of typical features shows typical distortion under various conditions.
Generally speaking, the second harmonic will control the distortion with the three harmonic components that can be ignored before the Kizai reaches a very high frequency or power. Then, focus on the second harmonic, increase the load impedance directly to improve the distortion. Remember that the total load includes the feedback network in non -invasive configuration, which is the sum of RF+RG, and in the reversal configuration, this is only RF (see Figure 1). Increased output voltage swing directly increases harmonic distortion. Increased output width 6db usually adds 2 harmonic 12DB and 3 harmonic 18DB. Increasing signal gain will also increase the second harmonic distortion. Increase 6DB, even if the output power and frequency are constant, it will increase the 2 or 3 harmonics of about 6DB. Finally, due to the frequency decay of the loop gain, the distortion increased with the increase of the infrastructure. On the contrary, the distortion will be improved to the main opening pole at a lower frequency at about 100kHz. Starting from -70DBC 2 harmonics (5MHz), 2VPP base waves have changed from G u003d+2 (from typical features) to 200 Essence
OPA656 has extremely low third -order harmonic distortion. This also shows the response curve of the third -order interoperability (IM3) of the two -color tone. At low output power levels, the third-order fake level is low ( lt; -80dbc). Even if the basic power reaches a higher level, the output phase remains low. Typical features show that false adjustment power does not increase as traditional interception model prediction. As the basic power level increases, the dynamic range has not significantly reduced. For 2 tones centered on 10mHz, 4dBM/sound to 50 load (that is, each tone 1VPP during load, the entire 2 audio package at the output pin requires 4VPP), typical feature display test sound tone sound tone tone 78DBC between the 3 -order fake level. This special performance is further improved when working under low -frequency and/or higher load impedance.
DC accuracy and offset control
OPA656 has the advantages of high opening gain, high co -modular suppression, high power suppression, high input bias voltage (drift), and small input bias currents, which can be ignored, which can provide excellent DC accuracy. In order to obtain the best DC accuracy, the high -level version (OPA65UB or OPA656NB) screens key DC parameters to a stricter limit. Both standards and high -level versions use new final test technology, and 100%test input bias voltage drift exceeds temperature. This discussion will be explained using advanced typical and minimum/maximum electrical characteristics; however, the standard -level version applies the same analysis.
The total output DC bias voltage at any configuration and temperature will be a combination of multiple possible errors. In the JFET part like OPA656, the input bias current items are usually very low, but they do not match. Use bias current offset technology, which is more typical in the bilateral input amplifier, and will not improve the output DC bias error. The error caused by the input bias current is only dominated at high temperature. OPA656 shows that the typical 2X increase of the JFET input -level amplifier per 10 ° C. With the maximum test value of 5PA at 25 ° C and self -heating within 20 ° C (see thermal analysis), the maximum input bias current in the 85 ° C environment will be 5Pa #8226; 2 (105–25)/10 u003d 1280Pa Essence For non -vertical configuration, this term only starts the effective item of the input bias voltage of source impedance gt; 750K This will also be the feedback resistance value of the transient application (see Figure 3). Among them, the output DC error caused by the inverter input bias current is based on the contribution order of the input bias voltage. Generally speaking, in addition to these high impedance values, the output DC error caused by the input bias current can be ignored.
After the input bias voltage itself, the most impact on the output bias voltage is the PSRR of the negative power supply. The term is modeling as the input bias voltage offset caused by changes in negative power voltage (and+PSRR). - PSRR's high -level test limit is 62DB. This is converted to 1.59mv/V input bias voltage shift u003d 10 (–62/20). In the worst case, the offset of ± 0.38V (± 7.6%) of the negative power voltage will generate a visual input bias voltage offset of ± 0.6mV. Because this is equivalent to the test limit of ± 0.6mv input bias voltage, the negative power supply voltage needs to be carefully controlled. +PSRR test to minimum value 74db. This is converted into 10 (–74/20) u003d 0.2mv/V sensitivity of the input bias voltage.
For example, calculate the worst output DC error in the transient circuit under 25 ° C in Figure 1, and then offer the following assumptions from the offset from the range of 0 ° C to 70 ° C.
Negative power supply
u003d -5V ± 0.2V, with the worst-shifting positive power supply with ± 5mv/° C
123] u003d+5V ± 0.2V, with the worst case of ± 5mv/° C in the worst case, the initial 25 ° C output DC error band
u003d ± 0.3mv (because - psrr u003d 1.59mv/v #8226; ± 0.2v)
± 0.04mv (because+PSRR u003d 0.2mv/V #8226; ± 0.2V)
± 0.6mv input bias voltage
Total u003d Total u003d ± 0.94mv
This will be the worst error zone in mass production under the test conditions of 25 ° C.
In the temperature range of 0 ° C to 70 ° C, we can expect that the worst situation below is transferred from the initial value. It is assumed that it is heated by the 20 ° C internally.
± 0.36mv (OPA656 Advanced input offset drift) u003d ± 6 μV/° C #8226; (70 ° C+20 ° C –25 ° C))
± 0.23mv ( - PSRR, 5MV #8226; (70 ° C – 25 ° C) Power Switch)
± 0.06mv (+PSRR is 72DB, 5mv #8226; (70 ° C – 25 ° C) Power supply Switch)
Total u003d ± 0.65mv
This will be the worst case from the initial offset exceeding 0 ° C to 70 ° C under the prescribed conditions. The typical initial output DC error band and temperature drift will be greatly lower than these worst cases.
In the transient configuration, because the input co -mode voltage is kept on the ground, the CMRR error can be ignored. For non -vertical gain configuration (see Figure 1), CMRR items need to be considered, but it is usually far below the input bias voltage item. In the case of testing minimum 80db (100 μV/v), Figure 1 Circuit ± 2V input swing increased to the DC error of not more than ± 0.2mV.
Power Note
OPA656 is used for operations on ± 5V power. The single power supply operation is allowed to change from the specified specifications and performance from a single+8V to+12V to the maximum value. The restriction of the power supply voltage operation is the input voltage range available for the JFET input level. There are many advantages from+12V's single power operation. In the case of negative power supply, the DC error caused by the -PSRR item can be minimized. Generally, during the+12V operation, the AC performance is slightly improved, and the power supply current increases to the minimum.
Hot analysis OPA656 does not require heat dissipation or airflow in most applications. The maximum allowable knot temperature will set the maximum internal power consumption, as described below. In any case, the maximum connection temperature shall not exceed 150 ° C.
Work knot temperature (TJ) From TA+PD #8226; θ
JA gives. The total internal power consumption (PD) is the sum of the additional power consumed by static power (PDQ) and output phase (PDL) to provide load power. Static power supply is only the specified air supply current multiplication by the total power voltage of the entire component. PDL will depend on the required output signals and loads, but for the ground resistance load, when the output is fixed at a voltage of 1/2 of the voltage of any power supply (for the two -pole power supply), the PDL will be at the maximum value Essence Under this condition, PDL u003d vs2/(4 #8226; RL), where RL includes feedback network loading.
Note that it is the power during the output stage rather than the load determines the internal power consumption.
As the worst example, the maximum TJ is calculated in the OPA65N (SOT3-5 package) in Figure 1. load.
pd u003d 10V #8226; 16.1MA+52/(4 #8226; (100 | 800 ) u003d 231MW
maximum TJ u003d+85 ° C+( 0.23W #8226; 150 ° C/W) u003d 120 ° C.
All actual applications will run at lower internal power and knot temperature.
Board layout
If you want to get the best performance, use high -frequency amplifiers like OPA656, you need to pay close attention to the plate layout parasitic and external component types. Suggestions that optimize performance include:
a) minimize parasitic capacitors to any communication ground to all signal I/O pins. The parasitic capacitor on the output end and the inverter input pins will cause unstable input unstable input, it will react with the source impedance, causing unintentional limits. In order to reduce unnecessary capacitors, the window around the signal I/O pin should be opened on all ground and power plane. Otherwise, ground and power aircraft should be uninterrupted elsewhere on the ship.
B) Minimum distance ( lt; 0.25 "") from power pins to high -frequency 0.1U F decoupled capacitor. At the device pin, the ground layout of the ground and power supply should not be close to the signal I/O pin . Avoid narrow power and ground traces, to minimize the inductance between the coupling capacitors. The power connection should always be decoupled with these capacitors. More (2.2 μF to 6.8 μF) of the counter -coupling capacitor should be valid at low frequencies. It is also applied to the power pin. These can be placed in a slightly far away from the device and can be shared between multiple devices in the same area of u200bu200bthe PC board.
C) Careful selection and placing external components will be carefully selected and placed. Maintain the high -frequency performance of OPA156. The resistor should be a very low -power resistance type. The surface installation of the resistor is best to work, and allows a closer overall clothInning. Metal film and carbon component axial binding resistance can also provide good high -frequency performance. Similarly, keep the wire and PCB tracking length as short as possible. In high -frequency applications, do not use a wire winding resistor. Because the output pins and inverter input pins are the most sensitive to the parasitic capacitance, the feedback and tandem output resistors (if so) should be as close to the output pin as much as possible. Other network components, such as non -rotating input terminal connection resistors, should also be placed near the package. If the double -sided component is allowed to install, the feedback resistor is directly placed directly below the package on the other side of the board, located between the output end and the reverse input pin. Even when the low -parasitic capacitor diversion the external resistor, the high resistance value will generate significant time constant, thereby reducing performance. A good axial metal film or surface unloader is about 0.2pf when the dial -resistor is connected to the resistor. For the resistance value gt; 1.5k , the parasitic capacitor can add a pole and/or zero to the circuit operation below 500 MHz. Keep the resistance value as low as possible to meet load driving considerations. It is recommended that a good starting point for design is to keep RF | RG LT; 250 and for voltage amplifier applications. This will automatically maintain the impact of low -resistance and minimize its parasitic capacitance. As long as you consider all the parasitic capacitance items on the inverter node set up feedback compensation capacitors, the transient application (see Figure 3) can use any feedback resistor required by the application.
D) The connection with other broadband devices can be tracked directly on the board or through the vehicle transmission line. For short connections, the input of tracking and the next device is considered as a collection of total capacitance loads. It should be used with relatively wide marks (50mils to 100mils), and it is best to open the ground and power plane around the surroundings. It is estimated that the total capacitance load and set the RS are estimated in the graph of RS and capacitor load. Low parasitic capacitance load ( lt; 5PF) may not require RS because OPA656 is compensated to run with 2PF parasitic load. If long tracking is required, it is allowed to increase the signal gain (increased the load phase margin), allowing higher parasitic capacitors without RS, and the inherent 6DB signal loss of the double -end transmission line is acceptable. Or with a line technology to achieve the matching impedance transmission line (see the ECL micro -band and the line layout technology design manual). Generally, the environment does not need 50 in fact, the high impedance environment will improve distortion, such as distortion and load charts. According to the feature board tracking impedance defined by the plate and tracking dimension, the matching string resistor and the destination device input end -connected resistor are connected to the matching of the tracker from the output of OPA656. At the same time, the end-connected impedance will be a parallel combination of parallel resistance and target equipment input impedance-this total effective impedance should be set to match the tracking impedance. If the 6DB attenuation of the dual -end transmission line is unacceptable, the long tracking can only be terminated in series at the source end. In this case, the tracking is considered as a capacitor load and a series resistance value is set,Discuss the diagram of the RS and the capacitor load. This will not maintain signal integrity and double -end lines. If the input impedance of the target device is low, the signs formed by the sideline formed by the series output will generate a signal attenuation to enter the terminal impedance.
E) High -speed parts such as OPA656 are not recommended. The additional lead length and capacitance of the socket can produce a very troublesome parasitic network, which is almost impossible to achieve a stable and stable frequency response. Welded OPA656 to the board to get the best results.
Input and ESD Protection
OPA656 is built on a very high -speed complementary bipolar process. For these very small geometric devices, the internal cutting voltage is relatively low. These segments are reflected in the absolute maximum rating table. As shown in Figure 5, all device pins are protected by the internal ESD to protect the power supply. 