Features

1024 -bit disposable programming (OTP) EPROM, used to store user programming data

Factory programming No.

reduce the single-line interface of circuit board wiring

synchronous communication reduces host interrupt overhead

15KV IEC 61000-4-4- 2 ESD compliance of the data pin

No need for backup power supply

provides 3 stitches SOT-23 and To-92 packaging

Application

Security encoding

Inventory tracking

Product revision and maintenance

Explanation

BQ2022A is a 1K serial EPROM, including the only 48 -bit identifier, 8 -bit CRC generation and 8 -bit series code (09h) of factory programming. 64 -bit state register control writing protection and page redirection.

BQ2022A SDQ #8482; The interface only needs to connect and one grounding loop. The data tube is also the only power supply for BQ2022A.

Small surface stickers and packaging schemes saves print circuit board space, and low costs make it ideal choice parameters, record maintenance, asset tracking, product revision status and access code security for applications such as battery packs.

(1), please refer to the available appetite at the end of the data table.

needle configuration and function

Typical features

] Detailed instructions

Overview

The functional frame diagram shows the relationship between the main control and memory part of the BQ2022A. BQ2022A has three main data components: 64 -bit factories programming ROM, including 8 -bit code, 48 -bit identifiers and 8 -bit CRC values, 1024 -bit EPROM and EPROM status bytes. The power supply of the reading and writing operation comes from the data tube foot. The internal capacitor stores energy when the signal line is at high, and the energy is released when the data tube foot is low, until the tube's foot returns the high position to supplement the charge on the capacitor. You can read the program configuration file by the special manufacturer to determine the programming configuration file required by programming components.

Function box diagram

Feature description

1024 -bit EPROM

Table 1 is the memory mapping of the 1024 -bit EPROM part of BQ2022A, which is configured to 4 pages, 32 bytes per page. The 8 -byte RAM buffer is an additional register used during memory programming. The data was first written into the RAM buffer, and then verified by reading 8 -bit CRC from BQ2022A to confirm the correct reception of the data. If the content of the buffer is correct, a programming command is issued and the 8 -byte data segment is written into the address selected in the memory. This process ensures the data integrity of memory programming. See the memory/status function command of the 1024 -bit EPROM section of BQ2022A for reading and programming BQ2022A.

EPROM status memory

In addition to the programmable 1024 -bit memory, there are 64 -bit status information contained in the EPROM state memory. Status memory can be accessed through separate commands. The status bit is EPROM, which is read or programmed to instruct various conditions for the software of BQ2022A. The first byte of the status memory contains a protective page position. If it is programmed properly in the 1024 -bit main memory area, the corresponding page is prohibited from programming. Once a bit is programmed in the writing protective page bytes, the entire 32 -byte page corresponding to this bit cannot be changed again, but it can still be read. You can use the Write Status command to clear the writing protection position.

The lower four bytes of the EPROM status memory contain the page address redirection to the byte. The bit in the EPROM status bytes can indicate the page of the byte to the page with an appropriate redirection to the host. The hardware of BQ2022A does not make decisions on the content of bytes based on the page address. This feature allows users to replace the page address to the page address to redirect the page in the byte by indicating that one or more specific pages should be replaced by the page address. A replacement code of the new page address to the page address corresponding to the original (replacement) page redirection to the byte. If the page address redirection has a FFH value to the byte, the data corresponding to the page in the main memory is valid. If the page address redirection has other hexadecimal values, the data corresponding to the page corresponding to the byte of the redirection to the byte is invalid. Valid data is found in the supplementary code of the page address of the indicator. For example, the FDH value in the byte indicates that the updated data is now located on page 2. The details of the EPROM status memory part of the reading and programming BQ2022A are given by the memory/status function command.

Error check

In order to verify the data sent from BQ2022A, the host generates the CRC value from the data when receiving the data. Be bornThe value of it compared with the CRC value sent by the BQ2022A. If the two CRC values match, there is no error transmission. The equivalent polynomial function of this CRC is X8+X5+X4+1. For details, see the CRC generation of this data table.

Custom BQ2022A

64 -bit ID identifies each BQ2022A. The 48 -bit serial number is the only one, programming by Texas Instruments. The default 8 -bit series code is 09h; however, you can retain different values according to a single customer. For more information, please contact your Texas Instrument Sales Representative.

The bus terminal

Since the driver output of BQ2022A is a leakage N-channel MOSFET, the host must provide a source current or 5-kΩ outer pull, as shown in the typical application circuit in FIG. 18 Show.

Equipment function mode

During the SDQ communication period or SDQ stays in an effective VPU voltage, the device is in the activation mode.

Programming

Serial communication

The host reads, programming or checking the status of BQ2022A through the command structure of the SDQ interface.

Initialization

Initialization consists of two pulses, reset pulse and existence pulse. The host generates a reset pulse, and the BQ2022A uses a pulse response. The host resets the BQ2022A by driving the data bus low at least 480 μs. For more details, see the reset and state pulse part.

ROM command

Reading the ROM command

Reading the ROM command sequence is the fastest sequence that allows the host to read 8 -digit code and 48 -bit identifier. Reading the ROM sequence starts with a reset pulse of at least 480 μs generated by the host. BQ2022A has a pulse response. Next, the host continues to send the ROM command 33h, and then use the reading signaling (see reading and writing signal parts) to read the ROM and CRC bytes during the data frame.

Skip the ROM command

This SKIP ROM command CCH allows the host to access the memory/status function. The SKIP ROM command is behind the Memory/Status Functions command.

Real/status functional command

Six memory/status functional commands allow read and modify 1024 -bit EPROM data memory or 64 -bit EPROM status memory. There are two types of read memory commands, plus writing memory, reading status and writing status commands. In addition, the component response program configuration file byte command. BQ2022A only responds to the memory after the part is jumped over the ROM command/Status function command.

Read the memory command

There are two read memory commands on the BQ2022A. Both commands are used to read data from 1024 -bit EPROM data fields. They are read storage/pages CRC and read memory/field CRC commands. Reading memory/page CRC generates a CRC at the end of any 32 -byte page boundary, while the read memory/field CRC generates a CRC when it reaches the end of the 1024 -bit data memory.

Reading memory/page CRC

In order to read the memory and generate CRC at the 32 -byte page boundary of the BQ2022A, follow the SKIP ROM command to read the memory/generate CRC command C3H, followed Low -byte, then the address high byte.

BQ2022A calculates the 8 -bit CRC of the command byte and the address byte by byte, and read it back by the host to confirm the receiving the correct commands and starting address. If the CRC reads is incorrect, the pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the host sends a read time clearance and receives data from the BQ2022A. From the initial address, it continues to the end of the 32 -byte page. At this time, the host sends 8 additional reading time gaps and receives an 8 -bit CRC. This is the result of migrating all data bytes from the beginning of the current page to the last byte CRC generator. Once you receive 8 -bit CRC, read the data from 1024 -bit EPROM data fields from the next page. This sequence continues until the host reads the last page and its attached CRC. Therefore, each page of data can be considered as 33 bytes, EPROM data and 8 -bit CRC with 32 -byte user programming, and automatically generate at the end of each page.

7.5.5.2 Read memory/site CRC

In order After the Read Memory command F0H, follow the address low byte, and then the address High byte.

Note: As shown in Figure 8, a single byte of the address and data is first sent by LSB.

BQ2022A calculates the 8 -bit CRC of the command byte and the address byte by byte, and read it back by the host to confirm the receiving the correct commands and starting address. If the CRC reads is incorrect, the pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the host sends a read time slot and receives data from the BQ2022A. From the initial address, it continues to the end of the 1024 -bit data field or until the reset pulse is issued. If you read at the end of the memory space, the host can issue eight amountsExternal reading time gap, and BQ2022A responds to 8 -bit CRCs of all data bytes read from the initial bytes of the memory to the last byte. After the host receives the CRC, before the reset pulse is emitted, any subsequent reading time slot is displayed as logic 1. Any reading ended by the reset pulse before reaching the end of the memory is available.

Write to the memory command

Write Memory commands to program to program 1024 -bit EPROM memory fields. The 1024 -bit memory field is programmed in 8 bytes. Data first write a 8 -byte RAM buffer at a time. Then, when a programming command is issued, the content of the RAM buffer is added with the content of the EPROM memory field.

FIG. 9 illustrates the event sequence of programming for EPROM memory field. After the SKIP ROM command is issued, the host issues a memory command 0Fh, and the low byte and high bytes of the starting address are followed. BQ2022A calculates and sends 8 -bit CRC based on writing commands and addresses.

If the CRC reads the CRC read at any time during the memory process, the reset pulse must be issued, and the entire sequence must be repeated.

After the BQ2022A sends a CRC, the host sends 8 -byte data to BQ2022A, and then calculates and sends 8 -bit CRC based on the 8 -byte data. If the CRC is consistent with the CRC calculated by the host, the host sends the program command 5AH, and then applies a programming voltage at least 2500 μs or TEPROG. Then, the content of the RAM buffer is logical and operational with the content of the 8 -byte EPROM of the start address.

The starting address can be any integer multiple of 8 between 0000 and 007F (Sixteen inlet), such as 0000, 0008 and 0010 (hexadecimal).

Write the data memory command sequence can be terminated at any point by sending a reset pulse, except during the period of the program pulse cycle TPROG.

Note: BQ2022A first responded to the minimum effective digit data from the selected EPROM address. This response should be checked to verify the programming bytes. If the programming bytes are incorrect, the host must reset the part and start writing the sequence.

For these two situations, the decision of continuing programming is completely made by the host, because BQ2022A cannot determine whether the 8 -bit CRC calculated by the host is consistent with the 8 -bit CRC calculated by BQ2022A.

Before programming, the bit in the 1024 -bit EPROM data field was displayed as logic 1.

Reading status command

Read Status command is used to use EPROM Status DATA field read data. After the SKIP ROM command is issued, the host issues the read status command AAH, then the address low byte, and then the address high byte.

Note: BQ2022A calculates the 8 -bit CRC of the command byte and the address byte by byte, and reads it back by the host to confirm the receiving the correct command and the start address.

If the CRC read by the host is incorrect, it must emit a heavy pulse and the entire sequence must be repeated. If the CRC received by the host is correct, the host sends a read time clearance and receives data from the BQ2022A, starting from the address provided and continued to reach the end of the EPROM status data field. At this time, the host receives 8 -bit CRC, which is the result of migrating all data bytes from the initial byte to the CRC generator containing a 00H value.

The reason why this feature is provided is because the EPROM status information may change over time, making it impossible to program data once, and including always effectively accompanied CRC. Therefore, the Read Status command provides an 8 -bit CRC that is consistent with the current data stored in the EPROM Status Data field based on (and always with).

After reading 8 -bit CRC, the host received logic 1s from BQ2022A until the reset pulse was issued. Reading status command sequence can end at any point by sending a reset pulse.

Writing status command

The writing state command is used to program the EPROM status data field after sending the BQ2022A to skip the ROM command.

The flow chart in FIG. 11 indicates that the host sends a state of writing status command 55h, then the address is low byte, then the address is high byte, and finally the data by.

Note: The single byte of the address and data is first transmitted by LSB. The 8 -bit CRC of the command byte, the address byte and the data byte by the data by the data by the data by the data is calculated by the BQ2022A and read it back by the host to confirm the receiving the correct commands, starting address and data bytes.

If the CRC read by the host is incorrect, it must emit a heavy pulse and the entire sequence must be repeated. If the CRC received by the host is correct, the program command (5AH) is issued. After sending a program command, the program voltage VPP is applied to the data tube foot to periodic TPROG. Before programming, the first seven bytes of the EPROM status data field are displayed as logic 1. For each bit of logic 0 provided by the data by the host, after the byte position is applied to the programming pulse, the corresponding bit programming in the byte of the selected by the EPROM status data field is logic 0. The eighth bytes of the EPROM status byte data field are programmed in the factory to include 00h.

After the application programming pulse and the data cable returned to the VPU, the host issued eight reading time slots to verify whether the appropriate position had been programmed. BQ2022A first responded to the minimum valid bit of data from the selected EPROM status address. This response should be checked to verify the programming bytes. If the programming byte is incorrect, the host must reset the device and start writing the sequence. If the BQ2022A EPROM data byte programming is successful, the BQ2022A will automatically increase its address counter to select the next byte in the state memory data field. The minimum effective bytes of the new dual -byte address are also loaded into the 8 -bit CRC generator as the starting value. The host uses eight writing time slots to send the next byte data.

When BQ2022A receives the data of the byte into the RAM buffer, it also transferred the data to the CRC generator. The CRC generator has already loaded the current address LSB. As a result, the new data is new data 8 -bit CRC and new address LSB. After providing data bytes, the host reads this 8 -bit CRC from BQ2022A, which has eight reading time slots, to confirm the correct increase of the address and the data bytes are correctly received. If the CRC is incorrect, the reset pulse must be emitted and the writing state command sequence is restarted. If the CRC is correct, the host issues a programmatic pulse and programming the byte selected in the memory.

Note: The initial writing of the status command is written to generate an 8 -bit CRC value. This value is to move the command byte to the CRC generator, then the two address bytes, and finally the data of the data. The result of byte. As BQ2022A automatically increasing its address counter, the subsequent writing in the writing state command will generate 8 -bit CRC, which is to load (non -shifting) of the LSB of the new (incremental) address to The results of the new data byte.

For these two situations, the decision of programming the EPROM status register is completely made by the host because the BQ2022A cannot determine whether the 8 -bit CRC calculated by the host is consistent with the 8 -bit CRC calculated by BQ2022A. If the wrong CRC is ignored and the host application pulse, incorrect programming may occur in BQ2022A. It should also be noted that BQ2022A always increases its internal address counter after receiving eight read time slots used to confirm the selected EPROM byte programming. The continued decision is completely made by the host again. Therefore, if the EPROM data bytes do not match the data bytes provided, but the host continues to execute the writing status command, it may occur in incorrect programming in the BQ2022A. You can end the writing state command sequence at any point by sending the reset pulse.

Program configuration file byte

Read the program configuration file bytes to determine the writing required by specific manufacturersMemory programming sequence. After the ROM command is issued, the host issues the Program Profile byte command 99h. Figure 12 shows that BQ2022A responds 55h. This will notify the host, which is written into the sequence described in the memory command section of the memory table.

SDQ signal Starting frame for position. FIG. 13 shows the initialization period, and Figures 14 and Figure 15 show that the host starts each bit by driving the data bus low in the starting cycle TWSTRB/TRSTRB. After the start, the host continues to control the bus during the writing period, or the BQ2022A responds during the reading period.

Rebate and Pulse

If the data bus is driven by more than 120 μs, the BQ2022A can be reset. FIG. 13 shows that if the data bus is driven by more than 480 μs, the BQ2022A reset, and it is ready to indicate it through the response to the existence.

Writing in the position

Figure 14 The writing sequence diagram shows that the host passes the twstrb part of the position, and then drives the data bus low level at low level Write 0, or release the data bus for writing 1 to start transmission.

Reading position

FIG. 15 The preface diagram displayed the host's transmission of the starting bit through the trstrb part of the position. Then, the BQ2022A uses the driver data bus low to send read 0 or release the data bus to send a read 1 to respond.

Program pulse

IDLE

If the bus is in high level, the bus is in a free state. The bus transaction can be suspended by allowing the data bus to be idle. Bullet transactions can be recovered from idle at any time.

CRC generation

BQ2022A has an 8 -bit CRC, stored in the highest effective bytes of 64 -bit ROM. The main control of the bus can calculate a CRC value from the top 56 -bit of 64 -bit ROM, and compare it with the value stored in BQ2022A to determine whether the bus main control has received ROM data without mistakes. The equivalent polynomial function of the CRC is: X8+X5+X4+1.

In some cases, BQ2022A also uses the same multi -ititage function just displayed to generate an 8 -bit CRC value, and provides the value to the bus host to verify the commands, addresses and data from the bus host to the BQ2022A. Byte transmission. BQ2022AIn order to write the memory and write status command, the value is output to the main control of the bus to confirm the correct transmission. Similarly, BQ2022A Calculates the 8 -bit CRC command to read the 8 -bit CRC commands for reading memory, reading status, and reading data by the bus host to confirm that these bytes have been accepted correctly. During reading data/generating 8 -bit CRC commands, each page of 1024 -bit EPROM data is sent to the main device of the bus, the CRC generator on the BQ2022A is also used to provide verification without error data transmission, as well as for status memory Verification of 8 -byte information in the field.

In every case when using CRC for data transmission verification, the main point node of the bus must use the previously given polynomial function to calculate the CRC value, and the calculation value and the 64 -bit ROM part stored in BQ2022A (use for use The 8 -bit CRC value in ROM) is compared with the 8 -bit CRC value calculated in the BQ2022A for comparison CRC values and the decision of continuing operations. If the value of the CRC and the bus node calculated by BQ2022A or BQ2022A does not match the value of the BQ2022A, any circuit on the BQ2022A will not prevent the command sequence from continuing. Correct use of CRC can produce a highly complete communication channel.

Application and Implementation

Note: The information in the following application parts is not part of the TI component specification. TI does not guarantee its accuracy or integrity Essence TI's customers are responsible for determining whether the part is suitable for its purpose. Customers should verify and test their design implementation to confirm the system function.

Application information

The typical application includes a microcontroller configured as a SDQ communication host device and the BQ2022A as the SDQ device. The host and the slave have a leakage function. To this end, a pull -up voltage of a pull -up resistor (usually 10 kΩ) is connected to the 2.65 V to 5.5 V range.

Typical application

SDQ line does not require additional capacitance, which may cause communication failure.

Design requirements

Detailed design program

Programming circuit example

BQ2022A requires 12 volts of maximum pulse signals to program OTP memory. It is necessary to set a programming test for production. Figure 19 shows what the circuit that may be set. The programming module contains the microcontroller of the SDQ host and controls the time and width of the programming pulse. 12 volt power is the power supply of programming pulse. Only the SDQ and VSS signals need to exit the test settings, because the application circuit containing the measured BQ2022A is only connected to programming and verifying data.

Programming modeBlocks are usually connected to PC with USB interfaces. The charts in Figure 19 do not include interfaces with the PC, which can change according to the selection of system designers.

SDQ master best practice

You may need to bit bang " on the host system to act as an SDQ host. In this case