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2022-09-20 05:00:00
ADF7021 is a high -performance narrow belt receiving chip Ⅱ
Precautions for the dissolution device
2FSK front guide code
The recommendation precrious code bit mode of 2FSK is a DC mode (such as 10101010 ... mode). You can also use the long -term length constraint (such as 11001100 ...), but it will lead to the longer synchronization time of receiving than the special flow in the receiver. The front guide code needs to be allowed to be used for the AGC processing of the receiver and CDR capture. It is recommended to have at least 16 front guide codes. When the receiver uses internal AFC, the recommended minimum front guide code is 48.
The remaining fields behind the front dock do not need to use DC codes. For these fields, ADF7021 can accommodate an encoding scheme with up to 8 digits without reducing performance. If you need a longer running length, it is recommended to use 8B/10B or Manchester encoding scheme.
4FSK front guide code and data encoding
The recommendation precrious code bit mode of 4FSK is repeated 00100010 ... sequence. This level 2 repeated 3,+3, -3,+3 symbol sequences are no DC, and maximize the time and data recovery of the symbolic timing of the 4FSK front guide code in the receiver. The minimum recommended length of the front guide code is 32 -bit (16 symbols).
The remaining parts of the 4FSK packet in order to insert a specific DC equilibrium symbol in the sending bit flow by using data chaos and/or in a fixed interval (for example, after 8 or 16 symbols). The symbol is close to the characteristics of no DC.
2FSK related demodulator and frequency error
ADF7021 has many options to fight the frequency error that exists due to the non -matching between transmission and receiving crystals/TCXOS.
In the case of disable AFC, the related demodulator can tolerate more than ± 0.4 × FDEV range error, where FDEV is the FSK frequency deviation. For larger frequency errors, by adjusting the K value, the bandwidth of the correor can be doubled, and the frequency tolerance can be expanded to ± 0.8 × fDEV. Calculation K is:
Use the new K value to re -calculate the BW settings of the discriminator. In this way, the bandwidth of the relevant device is doubled to increase the frequency error tolerance. The sensitivity loss of the receiver is 1DB to 2DB.
Related Small and Low -Dimmetrical Index
The modulation index in 2FSK is defined as:
[12]3] Use the new K value to re -calculate the discriminator. Figure 26 highlights that under the low -conditioning index, by doubled the bandwidth of the relevant device, the improvement sensitivity of the 2FSK modulation can be achieved. 
ADF7021 also supports the real -time AFC loop, which is used to eliminate the frequency error caused by incompatibility between transmission and receiving crystals/TCXOS. The AFC loop uses linear frequency blocks to estimate the frequency error. The output of a linear FSK discriminator has been filtered and average to eliminate the FSK frequency modulation. Use a combined average filter and an envelope detector. In the receiving mode, the output of the package detector provides an average frequency estimate.
AFC supported by ADF7021 has two methods: external and internal.
External AFC
Here, the user reads frequency information through the ADF7021 serial port, and applies the frequency correction to the score N synthesizer N splitter.
The frequency information is obtained by reading 16 -bit AFC Readback, as described in the Readback Format, and applies the following formulas:
Although the AFC_READBACK value is a symbolic number, it is positive under normal working conditions. In the absence of frequency errors, the frequency reflection value is equal to the medium frequency of 100 kHz. 
ADF7021 supports real -time, internal, and automatic frequency control circuits. In this mode, the internal control circuit automatic monitoring frequency error, and use the internal proportional integral (PI) control loop to adjust the synthetizer N splitter.
Internal AFC control loop parameters are controlled in the register 10. Activate the internal AFC circuit by setting R10 μDB4 to 1. Enter the proportional coefficient according to the crystal frequency of use. This is set in R10_DB [5:16]. You can use:
The maximum AFC range 
However, when the RF_ is enabled by _2 (R1_DB18), the programming range is halved. Explain this decrease by doubled the maximum AFC range of programming.
The maximum AFC correction range recommended is ≤1.5 × IF filter bandwidth. If the maximum frequency correction range is set to gt; 1.5 × if bandwidth, then iThe attenuation of F filter will reduce the sensitivity of the AFC ring circuit.
When the AFC and AFC correction range close to the IF filter bandwidth, the neighborhood suppression (ACR) performance of the receiver will be reduced. However, because the scope of AFC correction is programmable, users can weigh the scope of correction and ACR.
When an internal or external AFC is used to eliminate AFC errors, you can further increase the sensitivity of the receiver by using IF-BW Bit (R4-DB [30:31]) to reduce the bandwidth of the IF filter.
Automatic synchronous word detection (SWD)
ADF7021 also supports automatic detection of synchronous or ID fields. To activate this mode, synchronization (or ID) must be programmed in advance to ADF7021. In the receiving mode, compare the pre -edited word with the Bit flow of receiving. When identifying an effective match, ADF7021 asserted the external SWD pin on the next RX clock pulse.
This function can be used to remind the microprocessor that the valid channel has been detected. It relaxes the calculation requirements of microprocessors and reduce overall power consumption.
The SWD signal can also be used to frame the receiving packet by maintaining a high level in the pre -programmed bytes. The length of the packet can be set in R12_DB [8:15].
You can configure the SWD tube foot status by setting R112_DB [6: 7]. R11_DB [4: 5] is used to set the length of Sync/ID, which can be 12, 16, 20, or 24 bits. The recommended value is 24 bits, which may occur during the rest of the recovery packet in the rest of the recovery package or when there is no noise/no signal in the input terminal of the receiver. The transmitter must first send the synchronous byte MSB, and finally send LSB to ensure that the receiver synchronizes byte detection hardware correctly align.
You can also program a error tolerance parameter. When the word up to 3 digits is incorrect, the parameter accepts effective matching.
Specify the error tolerance limit in R11_DB [6: 7].
Application information
mid -frequency filter bandwidth calibration
Mid -calibration mid -frequency filter at each time in the receiving mode to correct the bandwidth and filter of the bandwidth and filter due to changes in process changes caused The center frequency is wrong. Once the automatic calibration is activated by writing the register 5, no external intervention is required. According to many factors, such as filter bandwidth, receiving signal bandwidth, and temperature changes, users must determine whether rough calibration or fine calibration. For information on calibration, see if the IF Filter section.
The performance of the two calibration methods is shown in Table 21.
When to use rough calibration 
When to use fine calibration
In the case of receiving signal bandwidth very close to the IF filter bandwidth, it is recommended to perform fine filter calibrations when the unit is powered on each unit.
If: OBW+rough calibration gt; if_filter_bw
Among them: OBW is 99%of the bandwidth of the transmission signal. Rough calibration changes to 2.5 kHz.
If the filter BW is set by R4_DB [30:31].
Filter_cal_complete signal from Muxout (set up by R0_DB [29:31]) can be used to monitor the filter calibration duration or send a calibration signal. The coarse filter calibration is automatically executed before the essence filter calibration.
When to use a single fine calibration
In the application of the receiver multiple times in a short period of time, you only need to perform a fine calibration of the initial receiver power.
After the initial rough calibration and fine calibration, you can use Filter_cal_read Back Result (refer to the Filter Bandwidth Calibration Readback part) to read fine calibration through a serial interface. On the subsequent power supply UPS in the receiving mode, the filter is manually adjusted by the previous fine filter calibration results. This manual adjustment uses if_filter_adjust bit (R5_DB [14:19]) to execute only when the continuous uninterrupted power supply lasts in the receiving mode is short, and the temperature changes during this period ( lt; 15 ° C), this method is used before this method is used. Essence
If the filter changes with temperature
When calibration, the center frequency of the filter can change with temperature changes. If ADF7021 is used in applications that maintain the receiving mode within a long time, users must consider this change in the center frequency of the filter. This change is usually 0 ° C 0.7 kHz, which means that if the coarse filter calibration and the fine filter calibration of the fine filter at 25 ° C are the initial maximum error 85 ° C) The maximum possible change in the center frequency of the filter is ± 4.5 kHz. The total error is ± 5 kHz.
If the bandwidth occupied by the receiving signal is far less than the IF filter bandwidth, the change of the center frequency of the filter may not be a problem within the working temperature range. Or, if the IF filter bandwidth is not enough to tolerate the change of temperature, the periodic filter can be performed, orUse the temperature sensor on the film to determine when the filter is required by monitoring changes in the temperature.
LNA/PA matching
ADF7021 shows the best performance in terms of sensitivity, transmission power and current consumption, provided that the radio frequency input and output port and antenna impedance are appropriately matched. For cost -sensitive applications, ADF7021 is equipped with an internal RX/TX switch to facilitate the use of simple combination of passive PA/LNA matching network. Alternatively, you can use an external RX/TX switch such as ADG919, which produces a slightly improved receiver sensitivity and lower transmitter power consumption.
Internal RX/TX switch
FIG. 49 shows the configuration of ADF7021, of which the internal RX/TX switch is used with the LNA/PA matching network of combination. This is the configuration used on the Evaladf7021DB evaluation board. For most applications, the minor performance reduction from 1DB to 2DB caused by internal RX/TX switches is acceptable, which allows users to use the cost of saving the cost of this solution. The design of the combined matching network must take into account the status of the RX/TX switch, and compensate the network's electrical resistance in the TX and RX paths.
Before reaching an acceptable compromise scheme, this process usually needs to iterate multiple times. The success of the LNA/PA combination matching network for ADF7021 depends on whether the PCB has accurate electronic models. In this case, it is strongly recommended to use the appropriate CAD software package. To avoid this effort, a small shape factors reference design design ADF7021, including matching harmonious filter components. The design is a 2 -layer printed circuit board to minimize costs. 
FIG. 50 shows the configuration of using the external RX/TX switch. This configuration allows independent optimization and matching and filter networks in the sending and receiving path. Therefore, it is more flexible than the configuration of the internal RX/TX switch, and it is more difficult to design. PA uses the inductance L1 bias, while C1 blocks DC current. L1 and C1 form a matching network together to convert the source impedance to the best PA load impedance ZOPT_PA.
Zopt_-PA depends on various factors, if the required output power, frequency range, power supply voltage range, and temperature range. In the AN-764 application description, selecting appropriate ZOPT_-PA helps consume the TX current to a minimum, which contains many ZOPT_-PA values containing representative conditions. However, under certain conditions, it is recommended to obtain an appropriate ZOPT_PA value through load tensile power measurement. 
According to the antenna configuration, users may need to install a harmonious filter at the PA output place to meet the obsessive transmission requirements of the applicable government regulations. Harmonic filters can be implemented in various ways, such as discrete LC-Pi or T-class filters. Low -pass filter components, such as the LFL18924MTC1A052 produced by Murata Manufacturing Co., Ltd. (work for 915MHz and 868MHz bands), is an attractive alternative to discrete design. By adding a rumor filter to the receiving path, ADF7021 can be improved by ADF7021 to interfere with strong bands. In addition to separate design, SAFCH869mam0T00, Safch915mal0n00, DCFB2869MLEJAA-TT1 or DCFB3915MLDJAA-TT1, which are produced by Murata Manufacturing Co., Ltd., are all suitable for this purpose. Or, as described in Table 14, you can improve the blocking performance of ADF7021 by selecting one of the enhanced linear modes.
Image suppression calibration
The image channel in ADF7021 is lower than the required signal 200 kHz. Multi -phase filters inhibit the image with asymmetric frequency. The image inhibitory performance of the receiver depends on the degree of matching of i and Q signals, and the degree of orthogonal matching between them (that is, the distance between them is close to 90 °). Uncardial image inhibitory performance is about 29 decibels (450 MM). However, by finding the best I/Q gain and phase adjustment settings, this performance can be improved by 20 dB.
Using internal radio frequency source calibration
In the case of LNA power off, the low -electric frequency tone generated on the chip was applied to the mixer input terminal. LO is adjusted to reduce the tone at the image frequency, and it is attenuated by the image of the IF filter at the image frequency. Then use RSSI Readback to measure the power level of the tone. Adjust the I/Q gain and phase adjustment DAC (R5_DB [20:31]), and re -measure RSSI. Repeat this process until the gain of the minimum RSSI recovery level and the optimal value of phase adjustment, thereby maximizing the image inhibitory performance of the receiver.
The use of internal radio frequency sources can be used by the radio frequency that can be used for image calibration, and it is a few times the reference frequency. 
Infrared calibration can also be implemented using external radiation sources. The infrared calibration program is the same as the program used in the internal frequency source, but the radio audio tone is applied at the LNA input terminal.
Calibration procedures and settings
The infrared school standard algorithm provided by the simulation equipment company is based on a low -complexity two -dimensional optimization algorithm and can be implemented in an external microprocessor or microcontroller.
To enable the internal frequency frequency source, please set the infrared sources to the maximum level. Set the LNA to its minimum gain setting. If the internal power is used, the AGC is disabled. Alternatively, you can use external radio frequency sources.
The amplitude of the phase adjustment is set by using IR_PHASE_UADJST_UMAG bit (R5_DB [20:23]). This correction can be applied to the I channel or Q channel, depending on the value of IR_PHASE_ADJUST_DIRECTION (R5_DB24).
The size of I/Q gain is adjusted by IR_GAIN_UADJUST_MAG Bit (R5_DB [25:29]). This correction can be applied to i or Q channels, depending on the value of IR_GAIN_ADJUST_I/Q bit (R5_DB30), and IR_GAIN_ADJUP/DN BIT (R5_DB31) sets the gain and definition of gain or attenuation adjustment.
The calibration results are effective when the ADF7021 power supply voltage changes. However, the temperature has also changed. After the initial calibration is performed at -40 ° C,+25 ° C and+85 ° C, the typical curve of image inhibition with changes with temperature changes is shown in Figure 52. The internal temperature sensor on ADF7021 can be used to determine whether new infrared calibration is required.
Group structure and encoding 
For information about the front guide code structure and length required for various modulation schemes, see the receiver setting part. 
Table 22 lists the number of minimum writing required for the ADF7021 in the TX or RX mode. You can also write additional registers to make the device suitable for specific applications, such as setting synchronous byte detection or enabled AFC. When turning from TX to RX or vice versa, the user needs to switch the TX/RX bit and only write the register 0 to change the LO 100 kHz.
The recommended programming sequences sent and received are shown in Figure 54 and Figure 55, respectively. These graphs show the differences in the routine of TCXO and XTAL. 
Application circuit 
For the recommended component value, see the ADF7021 assessment board data table and an AN-915 application description, you can access it from the ADF7021 product page. Strictly follow the reference design plan to ensure the best performance of narrowband applications.
Serial interface 
The data first enters the register MSB on the upper edge of each clock (SCLK). The data is transmitted to one of the 16 locks on the rising along the SLE. The target lock is determined by the value of the four control bits (C4 to C1); these four control bits are the bottom 4 LSB, DB3 to DB0, as shown in Figure 2. Data can also be read on Sread Pin.
Reading Format
By writing effective control words into the register and enable the return position (R7_DB8 1) to start the recovery operation. Reading can start after the control word is locked by the SLE signal. When reading data, SLE must be kept at a high position. Each activity edge on the SCLK tube foot will be read on the Sream tube foot continuously, as shown in Figure 57, first starting from MSB. The data that appears in the first clock cycle after the lock operation must be ignored. After 16 times of reading, you need an additional clock cycle to return the Sream Pin to the three -state. Therefore, the total clock cycle is required for each recovery. After 18 clock cycles, the SLE is lowered.
AFC Reading
AFC Review the FSK signal that only linear or related demodals activates is valid. The AFC Readback value is formatted into a symbol 16 -bit integer containing the bit RV1 in place RV16, and is zoomed in according to the following formulas:
In the absence of frequency errors, the FREQ RB Equal to the medium frequency of 100 kHz. Note that in order to make the AFC recall of effective results, the input signal of the downward converted transition cannot fall from the bandwidth of the analog IF filter. Under low input signal levels, the average changes in the recovery value can be improved by average.
RSSI reads
The format of the read word is shown in Figure 57. It includes RSSI -level information (bit RV1 in place RV7), andCurrent filter gain (FG1, FG2) and current LNA gain (LG1, LG2) settings. The filter and LNA gain are encoded according to the definition of the register 9-AGC register. For signal levels below -100 DBM, the RSSI value measured on average can improve accuracy. The input power can be calculated based on the RSSI read value summary of the RSSI/AGC part.
Battery voltage/adcin/temperature sensor read
Measure the battery voltage at the pin of the pin. Reading information includes in the RV1 Rv7. This is also applicable to the voltage readings of ADCIN pin and temperature sensor. From the return information, you can use:
The temperature can be used:
It is effective when setting any other register. Silicon correction words are encoded in BCD formats in four quadrains. Product code (PC) expands the quarter -bit coding of RV16 from the three -position RV5. The revised code (RC) is encoded by an RV4 in place by an RV1 in place. The product code of ADF7021 is read back to PC 0x210. The currently revised code read is RC 0x4.
Filter bandwidth school is allowed to read 
As described in the register 5-IF Filter Setup register, program to R5_DB [14: 14: 19].
interface with microcontroller/DSP
Standard send/receiving data interface 
In the receiving mode, ADF7021 provides a synchronous data clock on the TXRXCLK pin. Receive data is available on the TXRXData pin. Use TXRXCLK to rising along the data time to timely data to microcontroller. Please refer to Figure 4 and Figure 5 for the time sequencing diagram.
In the 4FSK transmission mode, the MSB of the transmission symbol enters the data clock first rising along the data clock rising along the txrxclk footAdf7021. In the 4FSK receiving mode, the first MSB of the first valid load symbol is punch -in on the first negative edge of the data clock after the SWD, and must be poured on the next rising edge to the micro -controller. For the time -sequential map, see Figure 6 and Figure 7. 
In UART mode, the TXRXCLK pin is configured to input the transmission data in the transmission mode. In the receiving mode, the receiving data is available on the TXRXData pin, which provides asynchronous data interface. UART mode can only be used with over -sampling 2FSK. Figure 59 shows the possible interface of the UART mode with ADF7021 and the microcontroller. To enable this UART interface mode, set R0_DB28 to high. Figure 8 and 9 show the time -sequential diagram of the UART mode.
SPI mode
In the SPI mode, the TXRXCLK pin is configured to enter the transmission data in the transmission mode. In the receiving mode, the receiving data is available on the TXRXData pin. CLKOUT pinch provides data clocks in sending and receiving modes. In the transmission mode, the data is scheduled in ADF7021 on the edge of the clock. In the receiving mode, the TXRXDATA data pins are sampled by the single -chip microcomputer on the positive edge of the CLKOUT. 
ADSP-BF533 interface
Figure 61 gives a recommendation method with Blackfin #174; ADSP-BF533 interface. 
The calculation method of the radio frequency output frequency is as follows:
For direct output 
For the selected RF_, divide by _2 (db18)
In the MUXOUT diagram in FIG. 62, the Filter_cal_Complete indicates that it is thick or thick (if the filter is calibrated). When the digital lock detection indicates when the PLL is locked. RSSI_READY indicates that the RSSI signal is stable and can execute RSSI reading. Tx_rx gives DB in the registerThe state of 27 can be used to control the external TX/RX switch.
R_ counter and XTAL_ double the relationship are as follows:
If XTAL_DOUBLER 0,
If XTAL_DOUBLER 1,
When using an external crystal, set the xosc_enable to high. If an external oscillator (such as TCXO) with a CMOS level output enters the pin OSC2, set the XOSC U enable to LOW. If you use 0.8 V p-P-P-P-wave sine wave output to the external oscillator of OSC1, set the XOSC U enable to High.
Set VCO_ partial position according to Table 9.
VCO_ adjustment bit adjusts the center of the VCO operation belt. Each bit usually adjusts the VCO frequency band to 1%of the frequency of RF (if the radio frequency is divided by 2, then 0.5%).
Set the VCO_Delectoier to the external permit to use an external induction VCO, which provides a RF operating frequency of 80 Hz to 650 MMC. If the internal inductance VCO is used for operation, the bit is set to low.
2FSK/3FSK/4FSK frequency deviation is as follows:
Direct output
Enable RF _ Except _2 (R1_DB18)
Among them, tx_frequency_deviation is set by db [19:27], PFD is PFD frequency.
In the case of 4FSK, there are tones at ± 3 × frequency deviation and ± 1 × deviation. Power amplifier (PA) slowly rises at a programming rate (R2_DB [8:10]) until its programming level DB [13:18]. If the PA is enabled/disabled by the PA_ENABLE bit (DB7), it will be tilted up and down. If it is enabled/disabled by the TX/RX bit (R0_DB27), it will be accelerated and closed.
R-Cosine_ALPHA Set the rolling factor (Alpha) of the data filter of the string data to 0.5 or 0.7. By default, Alpha is set to 0.5, but it can increase the raised string filter bandwidth to provide less radical data filtering by using 0.7 Alpha. 
The baseband offset clock frequency (BBOS CLK) must be greater than 1 MHz and less than 2 MHz, of which
Set the demoder clock (DEMOD CLK) , Make 2 MHz≤Demod CLK ≤ 15 MHz, of which 
For 2FSK/3FSK, data/clock recovery frequency (CDR CLK) needs to be at (32 × data rate) Within 2%. For 4FSK, CDR CLK needs to be within 2%of the (32 × symbol rate). 
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