Features

Tracking enhancement function

Quick ""two -way"" input voltage feedback (1/v2 correction)

Class connected converter interface

Controller

Remote open/off control

Precisely adjustable output overput

Feedback circuit protection

Disclosure ( Holding off)

The saturation protection of the inductor

Low -start current (≤100 μA)

6 ma maximum working bias current

1%(@tj u003d 25 ° C) Internal reference voltage

-600/+800 MA totem rod driver

During the UVLO period, take the initiative to pull down

SO14 package

Application

PFC pre-adjustment device:

High-end AC-DC adapter/charger

desktop computer, server, network server

conforms to IEC61000-3-2-2 Or Jeita-MITI standard SMPS, more than 400 watts

Device description

L6563s is a current mode PFC working under the transition mode (TM) PFC Controller. Here comes the same pins as the previous generation L6563, and it provides better performance and additional functions. Highly linear multiplication and a special correction circuit can reduce the influenza of cross -power supply, allowing the extremely low to be within the large load range. The output voltage is internal reference voltage from the voltage mode error amplifier and (1%@tj u003d 25 ° C). By optimizing the stability function of the circuit (1/V2 correction) through the voltage, a proper technology is used in this integrated circuit, which greatly improves the transient response when the voltage of the line power supply and the surge (""two -way"") Essence In addition, IC provides options for tracking boost operations, that is, the output voltage is to change the tracking power voltage. This device includes the disabled function PFC pre -regulator for remote/control controls in the system as the main control regulator, and the PFC pre -regulator work as a subordinate regulator. In the increased voltage protection device, the integrated circuit also provides feedback circuit fault protection or setting errors under the transient conditions. Other vehicle protection functions allow power -offs to be saturated to be processed safely. The interface of the PWM controller provided by the PFC pre-regulator PWM controller is provided: the purpose is to stop running the PFC-level abnormality when the converter is stopped when the following situation occurs (feedback circuit failure, the iron heart saturation of the voltage sensor, etc. ), And disable PFC in the case of the light load of the DC-DC converterLevel to more easily adhere to the energy -saving specifications (Blue Angel, Energystar, Energy 2000, etc.). Totem polar output level can withstand 600 mm of Anyuan current and 800 mAh current, which is suitable for large MOSFET or IGBT drivers. Combining other functions and possibilities operations and ST's proprietary fixed shutdown time control, the device becomes an excellent solution for the SMP standard of 400W of 400W of EN61000-3-2 and Jeita-Miti.

电气特性

TJu003d-25至125°C，VCCu003d12 V，插脚GD和GND之间的COu003d1 nF，CFFu003d1μF和RFFu003d引脚VFF和1 MΩ between GND; unless there are other regulations.

1. Tracking the parameters of each other

2. The output of the multiplication is obtained by the following formulas: [

[ 123]

3. Tracking the parameters

Typical electrical performance

[ 123] Application information

overvoltage protection

Generally, the voltage control circuit keeps the output voltage VO of the PFC pre -regulator, which is close to its nominal value. Ratio settings. A's pin (PFC_OK) of this device is specifically used to monitor the output voltage separation resistor division (R3 high, R4 low, see Figure 35). This separator is used for usual. If the output voltage exceeds the preset value, the voltage at the pin of the needle will reach 2.5 V greater than the expected maximum VO. Example: VO u003d 400V, VOX u003d 434V, select: R3 u003d 8.8MΩ; then: R4 u003d 8.8MΩ · 2.5/(434-2.5) u003d 51,000 Euros. When this function is triggered, the gate driver is stopped immediately until the voltage on the pfC_OK drops below 2.4 V. Please note that R1, R2, R3, and R4 can have no constraints. The only standard is that both separators must sink from the output bus current that needs to be significantly higher than INV and PFC U OK pins.

Feedback fault protection (FFP)

The above OVP function processing ""normal"" overvoltage conditions, that is, due Essence If the overvoltage is generated by the feedback, for example, the upload of the upper resistance division (R1) cannot be disconnected, and the additional circuit behind the PFC U OK detects the gap between the voltage relative to the Pin INV. If the voltage gap is greater than 40 mv and OVP is activated, FFP triggers FFP,The door -driven activity stopped immediately, the device was closed, and its static consumption was reduced to less than 180 μA, and the power supply voltage of the IC was higher than the UVLO threshold. At the same time, do not spoil the lock of the needle vein as high level. The pulse width control lock memory is a minimum load that can provide 2.8 volt voltage output to 0.25 mA, and the atresia shut off of PWM is integrated in a class joint DC-DC converter, so that the entire unit is in the lock lock state. It is necessary to recover the input power supply to restart the system, so that the VCC voltage L6563S is lower than 6V, and one of the PWM controller is lower than its UVLO threshold. The pin PFC_OK doubles it as a function disabled for non -locking ICs: the voltage below 0.23V will turn off the IC and reduce it to below 2 mAh. In this case, PWM_ stops high impedance state with PWM locks. To restart the integrated circuit, the voltage needle is higher than 0.27 V. Please note that these functions not only provide complete protection or setting errors in the feedback circuit failure, but also prevent their own protection. An any one -resistance PFC U OK distributor faults short -circuit or disconnect or PFC_OK pin float will cause the IC and stop the pre -regulator.

Voltage feedback

The power -level gain of the power factor correctional pre -adjustator changes the voltage with the square of the input balance. The cross frequency FC of the entire loop gain is also because the gain has a single pole characteristic. This has led to a large amount of weighing in the design. For example, setting the gain of an error amplifier to FC u003d 20 Hz@264 VAC means that there is an FC 4 Hzhz under the 88 volt AC voltage, resulting in a slow control of the control dynamic. In addition, the slow control loop is limited by the output dynamic output of the multiplicator when the route or load changes rapidly. Select the sensor of the sensor to make the full load pass through the minimum line voltage conditions, and to a certain amount of maximum. However, the fixed current limit allows to enter excessive power in the high -voltage line, while the fixed power limit requires that the current limit is inversely proportional to the line voltage. The voltage feedback can compensate the change of the subdivation voltage and allow all the problems as much as possible. It includes exporting an internal current control loop that exports an input -balanced square voltage, the internal current control loop that enters the voltage input square/removal (1/V2 corrector) and the internal current control loop providing a current of the current (see Figure 36)

[

123]

The change of the voltage is the half sine amplitude of the export place of the multiplier (if the line voltage will be halved, vice versa), so vice versa of the output place of the multipliers. Make the current basis adapt to the new operating conditions (ideally) without calling an error amplifier. In addition, the loop gain will maintain a constant range in the entire input voltage, which greatly improves the dynamic performance of the low line and simplifies the ring design. In fact, the voltage that derives the voltage of the equal square root line is proportional to a form of integration, which has its own time constant. If the voltage is too small, the generated voltage willDue to a considerable number of ripples at the twice -power frequency, the distortion current benchmark (resulting in high THD and low power factor); if it is too large, there will be a considerable delay in setting the correct feedback amount. As a result, the excessive pre -regulator output voltage changes over and underwriting voltage of the large line. Obviously, this needs to be weighing.

L6563s uses a use of only two external components, which greatly reduces the power supply voltage of the weighing problem of this time constant. A capacitor CFF and a resistor RFF are grounded from the pin VFF (#5) to complete the internal peak. The internal peak maintenance provides a circuit with a DC voltage of the DC voltage (#3) that is equivalent to applying a rectified sine wave peak on the pin (#3). In this case, the voltage of the CFF will quickly rise through the low impedance of the internal diode; if the line voltage decreases, the internal ""power supply voltage decreases"" detector starts a low impedance switch, the switch will suddenly discharge the CFF to reach the new voltage level at the new voltage level Avoid long -term stability before. Therefore, an acceptable low -stable state ripple and low -speed inflammation can really achieve that there is a considerable owed or overflow on the output of the pre -regulator, just like no feed compensation. The twice power frequency (2 u0026#8226; FL) ripples appearing on the CFF are triangular, with peak-peak amplitude, and the approximate value is as follows:

Among them, FL is the line is the line frequency. Three harmonic distortion related to this three -time harmonic distortion is related to 2FL component amplitude amplitude amplitude:

Figure 37 shows a chart, which can help choose the maximum expected three harmonics based on the maximum expectations of the maximum expectations of the maximum expectations Waves are disturbed. Always connect RFF and CFF to if the pin is kept floating or directly connected, the IC will not be able to work normally.

The dynamic characteristics of the voltage feedback input (that is, the output of the multiplier) are limited with a voltage of 0.8 V (see Figure 36). Therefore Below 0.8 V. This helps the line voltage below the minimum specified value.

The THD optimizer circuit

L6563s is equipped with a special circuit that can reduce the switching input current (cross deformation) near the zero -cross point of the passing of the line voltage of the line. In this way, the THD (total harmonic distortion) of the current is quite reduced. One of the main reasons for this distortion is that the system cannot effectively pass the energy when the instantaneous wire voltage is very low. This effect is enlarged by the high -frequency filter capacitor behind the bridge rectifier, and it retains some residuals that cause the backbone voltage of the bridge rectifier diode to temporarily stop. In order to overcome this problem, the device forced the PFC to pre -process more energy to deal with more energy. The voltage of the line was over zero, compared with the instruction of the control loop. This will minimize the time interval of insufficient energy transmission and rely on the bridge after the high -frequency filter capacitor is carried. picture38 shows the internal box diagram of the THD optimizer circuit.