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2022-09-20 05:00:00
ADF7021 is a high -performance narrow belt receiving chip Ⅰ
Features
Low -power narrow -band transceiver; use the dual VCO frequency zone; 80 Mixh to 650 MMC; 862 Mixh to 950 MMCs; modulation solutions: 2FSK, 3FSK, 4FSK, MSK; spectral plastic surgery; Gaussian; Gaussian; Gaussian; Gaussian Helosu strings filter; support data rate; 0.05 kbps to 32.8 kbps; 2.3 V to 3.6 V power supply; programming output power: -16 dbm to +13 dBM, 63 steps; automatic PA ramp control; receiving machine sensitivity; 130 DBM, speed is 100 BPS, 2FSK; 122 dBM, 1 kbps, 2 FSK; 113 dBM, 25 kbps, upgraded string 2fsk; is applying for patents, the image on the film refuses to calibrate; Position ADC and temperature sensor; fully automatic frequency control loop (AFC); digital receiving signal intensity indicator (RSSI); integrated TX/RX switch; 0.1 μA leaking current in power disconnection mode.
Application
Low -cost wireless data transmission; remote control/security system; wireless metering; private mobile radio; wireless medical remote test service (WMTS); keyless entry; family automation; process and process and process of process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process and process of family. Architectural control; Passing machine.
General description
The range of FSK modulation and data filter options on the film allows users to have greater flexibility when selecting the modulation scheme, while meeting strict spectrum efficiency requirements. ADF7021 also supports dynamic switching protocols between 2FSK/3FSK/4FSK to maximize the scope of communication and data throughput.The transmission part contains a dual -voltage -controlled oscillator (VCO) and the low -noise score N locking loop with a low noise score of the output resolution of less than 1ppm. ADF7021 has a VCO and a VCO and a VCO with internal LC grooves (431 MMS to 475 MM, 862 MMS to 950 MMS) and an external inductance as part of the groove circuit (80 MMS to 650 MMC) VCO. Dual VCO design allows dual -band operations, users can emit and/or receive any frequency of internal inductive VCO support, or they can also launch and/or receive specific frequency band support supported by the external inductance VCO.
frequency -based PLL allows ADF7021 to be used for frequency -jumpering (FHSS) system. The operating frequency of the two VCOs is twice the base frequency to reduce the problem of bruises and frequency traction.
The output power of the transmitter can be programmed at 63 steps, from -16 DBM to +13 DBM, and has an automatic power slope control to prevent spectral splash and help meet regulatory standards. The radio frequency and modulation of the transceiver can use simple 3 -line interface programming. The working power range of the device is 2.3 to 3.6 volts, and power can be disconnected when not in use.
The receiver uses a low -inter -frequency structure (100kHz) to minimize power consumption and external components, but avoid DC offset and low -frequency flashing noise. The mid -frequency filter has a programmable bandwidth of 12.5 kHz, 18.75 kHz and 25 kHz. ADF7021 supports a variety of programmable features, including RX linearity, sensitivity and intermediate frequency bandwidth, allowing users to weigh the sensitivity and selectivity and current consumption of the receiver according to the application.
The receiver also has an automatic frequency control (AFC) loop that is applying for a patent. The ring has a programmable pull -in range and allows PLL to track the frequency error in the input signal. The receiver uses an IR calibration scheme that does not need to use an external RF source to apply for a patent.
The ADC on the film provides a recovery of integrated temperature sensor, external analog input, battery voltage and RSSI signals, which provides ADC in some applications. The temperature sensor is accurate to ± 10 ° C within the entire working temperature range of -40 ° C to+85 ° C. This accuracy can be improved by performing 1 calibration at room temperature and stored the results in memory.
Preface Figure
4FSK timing
In the 4FSK receiving mode, the SWD guarantee of the SWD guarantee in the special stream MSB/LSB Synchronize.
UART/SPI mode
By setting R0_DB28 to 1 to enable UART mode. Establish the SPI mode by setting R0_DB28 to 1 and set R15_DB [17:19] to 0x7. Transmission/receiving data clock is available on the CLKOUT pin.
Absolutely maximum rated value
t 25 ° C, unless there is another instructions.
greater than or equal to absoluteThe stress on the maximum rated value may cause permanent damage to the product. This is just a stress level; it does not imply that the product operates the conditions described in the operation part of this specification or the above conditions. Long -term operation that exceeds the maximum operation may affect the reliability of the product.
This device is a high -performance radio frequency integrated circuit, ESD rated value lt; 2KV, sensitive to ESD. Take appropriate prevention measures during handling and assembly.
Typical performance features
Frequency synthesizer 
] Reference Input
Veorium crystal oscillator circuit (see Figure 31) can use quartz crystals as PLL reference. It is recommended to use quartz crystals with frequency tolerances less than equal to 10ppm in narrow band applications. You can use quartz crystals with a tolerance greater than 10 ppm, but in order to meet the absolute frequency error specifications (for example, Arib STD-T67 and ETSI EN 300-220) must be compensated to the frequency error of the crystal.
The oscillator circuit is enabled by setting the R1-DB12 high. By default, it is enabled when power -on, and is disabled by reducing CE. The error in the crystal can be corrected by using the automatic frequency control function or adjusting the decimal -N value (see the n counter part).
oscillations need to oscillate at the correct frequency. Two parallel resonance capacitors are required. Their value depends on the specifications of the crystal. When selecting the value of the capacitor, make sure that the capacitor connected value of the capacitor added to the PCB rail capacitor is equal to the specified load capacitor of the crystal, which is usually 12 PF to 20 PF. The rail capacitor value ranges from 2 PF to 5 PF, depending on the circuit board layout. If possible, select capacitors with very low temperature coefficients to ensure stable frequency operation under all conditions.
Use TCXO reference
Single -end reference (TCXO, VCXO or OCXO) can also be used with ADF7021. For applications with absolute frequency accuracy of less than 10ppm, such as Arib STD-T67 or ETSI EN 300-220, it is recommended to use this method. There are two options for ADF7021 and external reference oscillator.
oscillator with CMOS output level can be applied to OSC2. By setting the R1-DB12 low, the internal oscillator circuit is disabled.
0.8 V p-P's oscillator can be coupled to OSC1 through 22 PF capacitors. Establish an internal oscillator circuit by setting the R1-DB12 high.
Programmable crystal partial pressure current
oscillatorThe bias current in the circuit can be configured between 20μA and 35μA by writing the XTAL_ bias position (R1U DB [13:14]). Increasing bias currents can make the crystal oscillator more power -on.
CLKOUT removal and buffer
The CLKOUT circuit obtains the reference clock signal from the oscillator part, as shown in Figure 32, and provides a label space of 50:50 to the clkout foot. Signal. CLKOUT signal is reversed relative to the benchmark clock. The average points between 2 and 30 are available. This division is in R1_ 这个 [7:10]. When power is powered, CLKOUT defaults to 8.
To disable the CLKOUT, please set the division to 0. The output buffer can drive up to 20pf, and there is 10%of the rise at 4.8MHz. Fast edges may lead to some bruises for output. A series resistance (1kΩ) can be used to slow down the edge of the clock to reduce these bruises in the clock frequency.
R counter
The 3 -digit R counter will refer to the input frequency of 1 to 7. The frequency division signal is provided as the benchmark clock to the phase frequency detector (PFD). Frequency settings to R1_DB [4: 6]. Maximize PFD frequency reduction N value. This will reduce the output of the output at a rate of 20 LOG (N) and reduce the emergence of bandal weight.
Register 1 defaults to R 1 when power is powered.
pFD [Hz] XTAL/R
Ring circuit filter
The circuit filter integrates the current pulse of the charge pump to form a voltage, the output of VCO output Tune to the required frequency. It can also weaken the strange level generated by PLL. The typical ring filter design is shown in Figure 33.
Design ring circuit, so that the ring road bandwidth (LBW) is about 100 kHz. This provides a good compromise solution between the inner phase noise and the bruises in the band. Increasing LBW too much reduces the time of jumping between frequencies, but it may cause insufficient bruises. The narrow loop bandwidth will cause a long time to achieve locking, and it will also cause higher power to fall into the adjacent channel. Use a loop filter design on the Eval-ADF7021DB evaluation board to obtain the best performance.
Free Design Tool Adispll can also be used to design a ring filter for ADF7021.
n counter
ADF7021 The feedback division in the phase ring is a 8-bit integer counter (R0_DB [19:26]) and a 15-bit δ-Δ scorer ( R0_db [4:18]). The integer counter is pCommon standard pulse swallow types in LLS. Set the minimum rectangle to 23. The score -score -frequency value provides a very fine resolution at the output end. Among them, the output frequency of the PLL is calculated as:
When you choose RF At the time of the device (VCO), this formula becomes:
integer n (maximum value 255) and decimal n (maximum value 32768/32768) Maximum N division. Therefore, the minimum PFD is:
For example, when working in Europe 868MHz to 870MHz band, PFDmin is equal to 3.4MHz.
The voltage regulator
ADF7021 contains four voltage regulators to provide a stable voltage for the device. The voltage of the rated regulator is 2.3 V. Regulator 1 needs to connect a 3.9Ω resistor between Creg1 and GND and a 100 NF capacitor, while other regulators need to connect a 100 NF capacitor between CregX and GND. When the CE is high, the regulator and other related circuits are powered on, and the total power supply current is 2mA. Specify the CE pin to disable the regulator, reduce the power current to less than 1 μA, and remove all the values saved in the register. The serial interface work through the power supply. Therefore, to write the device, users must have CE height and voltage voltage of the regulator. The regulator status (CREG4) can be monitored using a regulator from Muxout. 
Muxout pin allows access to various number points in ADF7021. The status of MUXOUT is controlled by R0_DB [29:31].
The regulator is ready
Regulator_ready is the default setting of Muxout after the transceiver is powered. The power -on time of the regulator is usually 50 μs. Because the serial interface is powered by the regulator, the regulator must be programmed at the ADF7021 under its nominal voltage. The status of the regulator can be monitored in Muxout. When the regulator on the MUXOUT is ready signal, you can start programming ADF7021.
Filter
MUXOUT can be set to Filter_cal_complete. This signal becomes lower during the calibration of the coarse medium frequency filter calibration and the fine medium frequency filter calibration. It can be used as a interrupt of microcontroller to send a signal of the medium frequency filter calibration. 
When the digital lock detection indicates when PLL is locked.
Lock detection circuit is located on PFD. When the phase error of the five consecutive cycles is less than 15ns, the lock detection setting is high. Lock detection keeps high level until the 25 NS phase error is detected at the PFD.
ready
Muxout can be set to RSSI_READY. This indicates that the internal analog RSSI has been stable and can perform digital RSSI reading.
Send/receive
tx_rx indicates that ADF7021 is in the sending mode or receiving mode. When in the transmission mode, this signal is low. When you are in the receiving mode, this signal is high. It can be used to control the external TX/RX switch.
Pressure -controlled oscillator
ADF7021 contains two VCO cores. The first VCO, internal inductance VCO, using internal LC slots, supporting 862 MMS to 950 MMC and 431 MMS to 475 MMC work frequency bands. The second VCO, the external inductance VCO, uses the external inductance as part of its LC slot, and supports 80 MHz to 650 MHz RF operating frequency bands.
In order to reduce the bruises, the operating frequency of the two VCOs is twice the frequency of radiation. The VCO signal is then divided into 2 in the synthesizer ring, giving the frequency required for the transmitter and the frequency of local oscillator (LO) required for the receiver. Except for 2 (RF divide by 2) outside the synthesizer ring, to allow operations from 431 MHz to 475 MHz frequency bands (internal inductance VCO) and 80 MHz to 325 MHz frequency bands (external inductor VCO).
VCO needs to have an external 22 NF capacitor between the CVCO pin and the regulator (CREG1) to reduce the internal noise.
Internal inductance VCO
To select the internal inductance VCO, please set R1_DB25 to logic 0. This is the default setting. 
According to the required operating frequency, the VCO is re -entered by programming VCO_ adjustment bit (R1_DB [23:24]). See Table 9 for details.
External inductance VCO
When using an external inductive voltage control oscillator, the center frequency of the voltage control oscillator is transformed by internal volume diode capacitors and external chip inductors, key lines and printing circuit boards The combination of the track is set to set. The external inductance is connected between L2 and L1 pins.
The relationship between the frequency of VCO and the total external inductance (chip inductance+PCB trajectory) is shown in Figure 37.
The PCB magnetic tract induction of the FR4 material is about 0.57nh/mm. Subtract this value from the total value to determine the correct chip electrical value.
Generally, a specific inductance value allows ADF7021 to work within ± 6%of the operating frequency of RF. When the RF_ is selected to be ± 3%when the RF_ is divided by _2 -bit (R1_DB18). For example, at 400 MMS, it is expected that the working range of a single electrical sensor (the range of VCO centered on 400 MM) is ± 24 MM (that is, 376 MM to 424 MM). 
VCO's tuning range is 0.2 V to 2 V. Choose an external inductance value to ensure that the VCO work is as close to the center of the tuning range as much as possible. This is particularly important for radio frequency lt; 200MHz, of which the VCO gain is reduced and existing lt; ± 6MHz.
VCO's operating frequency range can be adjusted by programming VCO_ adjustment bit (R1_DB [23:24]). This usually allows VCO to move up to up to 1%of the radio frequency.
To choose an external inductance VCO, set R1_DB25 to logic 1. Set VCO_ bias current according to the operating frequency (as shown in Table 9).
Selecting the best system performance channel
The interaction between the frequency pressure control oscillator frequency and reference frequency can cause the production of scores. When the synthesizer is in the score mode (that is, the RF VCO and the reference frequency are not an integer -related), at the offset frequency of the difference between the integer multiple and the VCO frequency corresponding to the reference frequency, San. 
Transmitter
RF output level
ADF7021 power amplifier (PA) is based on a single -end, controllable current, and leakage amplifier. Under the maximum frequency to the 50Ω load, it provides a current of up to 13 dBM.
The output current and output power of the power amplifier can be programmed in a wide range. The PA configuration is shown in Figure 38. Set output skills with R2_DB [13:18]]Rate.
The power amplifier is equipped with overvoltage protection, so that it has robustness under severe loss. According to the application, users can design a matching network for PA to display the optimal efficiency at the expected radiation output power level such as ring antennas or single -pole antennas. For details, see the LNA/PA matching part.
PA slope 
ADF7021 has a built -in PA slope configuration. As shown in Figure 39, there are eight slope rate settings, which are defined as a specific number of PA settings of each data bit cycle. PA via each of the 64 code levels, but the speed of each setting is different. Set the slope rate by configuring R2_DB [8:10].
If PA is enabled/disabled through PA_ENABLE (R2_DB7), it increases at a programming rate, but it is difficult to turn off. If PA is enabled/disabled by TX/RX (R0_DB27), it increases and decreased at programming rate.
PA bias current
If necessary, PA_ partial position (R2_DB [11:12]) helps adjust the PA bias current To further expand the range of output power control. If this function is not needed, it is recommended to use the default value of 9 μA. If the output power greater than 10 dBM is required, it is recommended to set the PA bias to 11 μA. Turn off the output level by reset the R2-DB7. 
ADF7021 supports 2FSK, 3FSK and 4FSK modulation. The implementation of these modulation schemes is shown in Figure 40.
Set the transmission data rate
In all the modulation modes except the sampling 2FSK mode, provide accurate clocks on the TXRXCLK pins to so as to use it in order The required data rate locks the data of the microcontroller to the sending part. The exact frequency of this clock consists of: 
Among them: XTAL is a crystal or TCXO frequency.
DEMOD_CLK_DIVIDE is a removing instrument that sets the clock clock (R3_DB [6: 9]). 
For more programming information, see the regulator 3-send/receiving clock register part.
Set FSK send deviation frequency
In all modulation modes, use tx_frequency_deviation bit (R2_DB [19:27]) to set the deviation from the central frequency.
The deviation of the center frequency (unit: Hz) is as follows:
For direct RF output,
For rf_ 2 Enable,
In 4FSK modulation, 4 symbols (00,01, 11,10) were sent in the form of ± 3 × fDEV and ± 1 × FDEV, respectively.
Binary frequency shift key control (2FSK)
Set the n value of the center frequency, and then switch it with the TXData cable. Use TX_FREQUENCY_DEVIATION bit R2_DB settings to set the deviation of the center frequency [19:27].
Select 2FSK by setting the modulation scheme position (R2U DB [4: 6]) to 000.
The minimum shift key control (MSK) or Gauss minimum shift key control (GMSK) is supported by selecting 2FSK modulation and using a 0.5 modulation index. Set the modulation index 0.5 deviation from 0.25 × transmission data rate by configure R2_DB [19:27].
Three levels of frequent keypoles (3FSK)
In the three -level FSK modulation (also known as correction dual binary FSK), binary data (logic 0 and logic 1) map Different frequencies, that is, carrier frequencies (FC), carrier frequency minus deviation frequency (FC-FDEV), and carrier frequency plus deviation frequency (FC+FDEV).
Logic 0 mapped to the carrier frequency, and Logic 1 mapped to frequency FC-FDEV or FC+FDEV.
Compared with 2FSK, this Bit-frequency mapping causes the transmission bandwidth to decrease, because some energy is removed from the radio frequency band and transmitted to the carrier frequency. Under the low -conditioning index, 3FSK has increased by 25%of the launch spectrum efficiency than 2FSK.
3fsk's position to symbol mapping uses a linear convolutional encoder to implement, which is also allowed to use Viterbi detection in the receiver. The frame diagram used to realize the sendsing hardware of the system is shown in Figure 42. The polynomial of the convolutional encoder used to realize the launch spectrum plastic surgery is:
Among them: P is a volume encoder polynomial; D is the unit delayed operator.
The digital pre-codeler with a transmission function 1/p (d) implements the inverse model 2 operation of the 1-D2 formation filter in the transmitter.
Table 10 shows the signal mapping of the input binary sending data to the level 3 convolution output. The convolutional encoder restricts the number of maximum sequences+1s or -1S to 2, and transmits the same number of targets+1s and -1S to the FSK modulation to ensure that the spectrum energy in the two RF bands is equal.
Select 3FSK by setting the modulation scheme (R2 DB [4: 6]) to 010. It can also be used with the filtering of littering string to further improve the spectrum efficiency of the transmitting signal.
Four levels of frequency shifting frequency key control (4FSK)
In the 4FSK modulation, the TX data is entered into one of the four possible symbols in the four possible symbols by entering the continuous input of TX data to the special stream. The spectrum efficiency of each sign (-3, -1,+1,+3) per symbol. Therefore, the symbolic rate is half of the input rate.
By the interval between minimized symbol frequency, 4FSK can have a high spectrum efficiency. The 4FSK bit to the symbol mapping is gray -encoded, as shown in Figure 43.
Internal deviation frequency (+fdev and -fDev) use tx_frequency_ deviations R2_DB settings [19:27]. The external deviation frequency is automatically set to three times the internal deviation frequency.
After sending the clock from the PIN TXRXCLK, it can be available after the register 3 in the power sequence of the receiving mode. After writing the first symbol of MSB to the register 3, the clock on ADF7021 is on the first clock pulse sent from ADF7021. For more timing information, see Figure 6.
Over -sampling 2FSK
In the over -sampling 2FSK, there is no data clock from the TXRXCLK pin. Instead, the transmission data at the TXRXData pin is sampled at a 32 -fold programming rate.
This is the only modulation mode that can be used for data transmission with the UART mode interface (more information, see the interface part of the microcontroller/DSP).
spectral plastic surgery
Gauss or Shengyu String filterWaves can be used to improve the launch spectrum efficiency. ADF7021 supports Gaussian filtering in 2FSK modulation (bandwidth time [BT] 0.5). Shengyu string filtering can be used for 2FSK, 3FSK or 4FSK modulation. The rolling coefficient (α) of the lift string filter has a programmable option of 0.5 and 0.7. Both Gaussian and Shengyu String filters are implemented with a linear phase digital filter structure. The parameters of the BT and Alpha filter are accurately controlled, and the launch spectrum is very stable at temperature and power change.
Gaussian frequency shift key control (GFSK)
Gaussian frequency migration key control to reduce the bandwidth of the transmitting spectrum occupation by using digital pre -filtering to the emission data. The BT accumulation of Gaussian filter is 0.5.
Gaussian filtering can only be used for 2FSK modulation. This is selected by setting R2_DB [4: 6] to 001.
Ascending string filtering
Lift string filtering provides digital pre -filtering for sending data by using the rolling coefficient (α) to 0.5 or 0.7. By default, Alpha is set to 0.5, but it can increase the raised bandwidth of the raised string filter by using Alpha 0.7 (set R2-DB30 to logic 1) to provide less positive data filtration. Shengyu string filtering can be used for 2FSK, 3FSK and 4FSK.
As shown in Table 11, the littering string filter is enabled by setting R2 DB [4: 6].
The modulation and filter options
Table 11 describes various modulation and data filter options.
1. MSK is 2FSK modulation, and the modulation index is 0.5.
2. The offset of the formation of the semi -stringbone band formed orthogonal shift key control (OQPSK) is equivalent to MSK on the spectrum.
3. GMSK is GFSK with a modulation index of 0.5.
Transmission delay
The transmission delay is sampled from the TXRXCLK signal signal to the bit/symbol to the delay time when the bit/symbol appears at the RF output. No data filtering is 1 bit. As shown in Table 12, the addition of data filtering adds further delay.
It is important that after the data clock is sampled to the last data bit, ADF7021 remains in the transmission mode to explain this delay. Keep ADF7021 in the sending mode. This ensures that all data sampled by the TXRXCLK signal appear at RF.
The delay number in Table 12 assumed positive TXRXCLK edges for sampling data (default). If you reverse TXRXCLK by setting R2 DB [28:29], you can add additional 0 to all values in Table 12.5 -bit delay.
Test mode generator
ADF7021 has many built -in test mode generators, which can be used to promote wireless link settings or radio frequency measurement. The complete list of supported mode is shown in Table 13. The data rate of these test mode is the programming data rate set in the register 3.
PN9 sequence is suitable