Features

* Integrated NV SRAM, RTC, crystal, power failure control circuit and lithium energy

* clock register and static RAM The interview is the same; these registers are located in 16 top RAM positions

* completely difficult to volatilize at all, running for more than 10 years to accurately electricity reset for more than 10 years

* Programmable Dog Timer and RTC Alert

* The annual, month, day, day, time, time, and seconds of bcd encoding Year

* Battery voltage level indicator logo

* Power failure writing protection allows 10%VCC power tolerance

[

123] * Before the first power is powered on, lithium energy disconnecting power is kept fresh

generally explained

ds1553 is a full function, compliance with 2000 2000 The real time clock/calendar (RTC) of the year (Y2KC) standard, with RTC alerts, watchdog timers, power -up reset, battery monitor, and 8K X 8 non -easy -to -miss static RAM. The user's access to all registers in DS1553 is completed by a byte range interface, as shown in Figure 1. The RTC register contains a 24 -hour BCD format century, year, month, day, day, time, time, and secondary data. The monthly and leap year automatically correct.

Detailed instructions

The RTC register in DS1553 was doubled into a interior and external collection. Users can directly access external sets. The clock/calendar update of the external storage set can be disabled and enabled to allow users to access static data. Assuming that the internal oscillator is opened, the internal set of the register will continue to be updated. This will happen regardless of the external register settings to ensure that it always maintains accurate RTC information.

DS1553 has interruption (IRQ/FT) and reset (RST) output, which can be used to control the CPU activity. When the RTC register value matches the alarm value of user programming, the IRQ/FT interrupt output can be used to generate external interrupts. When the device is powered by the system power supply, the interruption is always available, and it can be programmed to occur in the battery power supply as a system wake -up. IRQ/FT or RST output can also be used as a CPU watch dog timer. If the correct activity is not detected within the programming restrictions, monitor the CPU activity and activate interruption or reset the output. DS1553 is used to power out to detect the power failure or failure, and keep the CPU in a safe reset until the normal power supply recovers and stabilizesCertainly. RST output is used for this function.

DS1553 also contains its own power failure circuit. When the VCC power supply enters a super -different state, the circuit will automatically cancel the selection device. This function provides high data security during the unpredictable system operation of low VCC levels.

Packaging

DS1553 offers 28 -pin DIP and 34 -pin PowerCap modules. The 28 -pin DIP module combines the crystals, lithium energy and silicon in a packaging. The 34 -pin PowerCap module board is designed to connect to a separate PowerCap (DS9034PCX) contacts containing crystals and batteries. This design allows PowerCap to be installed on the top of DS1553P after completing the surface installation process. The installation of the power cap on the surface installation process can prevent the crystals and batteries from damaging the high temperature required for the return of the solder. The power cover is key control to prevent reverse insertion. PowerCap module and PowerCap are separated and packed in separate containers. PowerCap's part number is DS9034PCX.

Data reading mode

As long as the CE (chip enable) is low, we (write enable) high, DS1553 is in the reading mode. Equipment architecture allows access to any valid address location. Under the premise of satisfying the CE and OE access time, after the last address is input stable, the data input/output (DQ) pin of the TAA can obtain valid data. If you are not satisfied with the CE or OE access time, the latter of the latter (TCEA) or the output access time (TOEA) can be used in the chip. The status of the DQ tube foot is controlled by CE and OE. If the output is activated before TAA, the data cable will be driven to the middle state until TAA. If the address input is changed when the CE and OE maintains validity, the output data remains valid within the time of the output data maintained (ToH), but then it will be uncertain until the next address is visited.

Data writing mode

When we and CE are in active state, DS1553 is in the writing mode. The beginning of writing refers to the conversion of the latter occurrence of we or CE. The address must be maintained throughout the cycle. CE and we must return to at least non -active TWR before starting or writing cycle. The data in the middle must be effective TDS before the end of the writing, and it must be valid in the subsequent TDH. In typical applications, the OE signal is high during the writing cycle. However, if you carefully use the data bus to avoid the use of the bus, OE can be activity. If OE is low before the conversion is low, the data bus can be activated through the address input definition of reading data. The low conversion is opened, and then the output TWEZ is disabled after activation.

Data retention mode

5V device is completely accessible. Only when VCC is greater than VPF, the data can be written and read. However, when VCC is lower than the power failure point (VPF), the point of protection occurs, and the internal clock register and SRAM will be prevented from any visits. When VSO (battery power supply level) is lower than the battery switch point, the equipment power supply is switched from the VCC pin to the internal lithium battery. Before the VCC is restored to normal level, RTC operations and SRAM data are maintained from the battery.

When VCC is greater than VPF, the 3.3V device is completely accessible, and the data can only be written and read. When VCC is lower than VPF, access device is prohibited. If VPF is smaller than VSO, when VCC is lower than VPF, the device power supply switches from VCC to internal lithium batteries. If VPF is greater than VSO, when VCC is lower than VSO, the device power supply switches from VCC to internal lithium batteries. Before the VCC is restored to normal level, RTC operations and SRAM data are maintained from the battery.

When VCC is disconnected, all control, data and address signals must be powered off.

Battery life

DS1553 has a lithium power supply, which is designed to provide energy for clock activities and clocks and RAM data when there is no existence of VCC power. The capacity of this internal power supply is enough to power it up in the service life of the installation of the DS1553 device. For the purpose of standardizing, when the internal clock oscillator runs without VCC, the expected life of+25C is 10 years. Each DS1553 was transported from Dallas Semiconductor. Its lithium energy was disconnected, ensuring all energy capacity. When VCC is first applied to a level higher than VPF, lithium energy can be used for battery backup operations.

Internal battery monitor

DS1553 continuously monitor the battery voltage of the internal battery. Low battery power (BLF) bits of the sign register (1FF0H) are not written, and it should always be 0 when reading. If there is 1, the lithium energy consumed, and the contents of RTC and RAM are suspicious.

Powering and reset

Temperature compensation comparator circuit monitoring VCC level. When the VCC drops to the power failure, the RST signal (leaking) is pulled down. When VCC returns to normal level, the RST signal continues to be pulled down by 40 to 200 milliseconds. The power -on reset function is independent of the RTC oscillator, so it can work regardless of whether the oscillator is enabled.

clock operation

Table 2 and below paragraphs describe the operation of RTC, alarm and door dog function.

X Unused, read/write under the control of the read and write

AE Alert sign

ft the frequency Test bit

Y Unused, read/write, no writing and read position control

OSC oscillator starts/stop bit

ABE the alarm in the battery backup mode enable

[

123] W Writing in place

AM1-AM4 Alarm mask position

R Reading position

WF watch the door dog logo

Wds see the steering position of the door

AF alarm logo

BMB0 #241; BMB4 watch the door dog multiplication

0 0 read

[

[

[

[

[

123] RB0 #241; RB1 Seeing Dog Frequency Bit

BLF Low battery power sign

clock oscillator control

clock oscillator can stop at any time. In order to extend the service life of the backup lithium battery source, the oscillator can be turned off and the current consumption of the current battery can be used. OSC is MSB of the second register (1FF9H). Setting to 1 will stop the oscillator; set to 0 to start the oscillator. DS1553 is shipped from Dallas Semiconductor Corporation, the clock oscillator is closed, and the OSC bit is set to 1.

Reading Clock

When reading RTC data, it is recommended to stop the update of the external dual cushioning RTC register set. This allows the external register to enter the static state and allows reading data without changing the register value during the reading process. In this state, the normal update of internal registers will continue. When 1 write to the control register (1F8H) reading B6, the external update stops. As long as 1 keeps in the control register read position, the update stops. After the HALT is issued, the register reflects the current RTC count (day, date and time) when the Halt command is issued. The normal update of the external register set is restored within 1 second after the read position is set to at least 500 seconds. Reading positions must be at least 500 seconds to ensure that external registers are updated.

Set the clock

The 8th place B7 of the control register is written. Set the position to 1, just like the reading position, stop updating the DS1553 (1ff8h 1ffh) register. After setting the position to 1, you can load the RTC register in a 24 -hour BCD format in a 24 -hour BCD format. Set the position to 0, then transmit the value of the internal RTC register, and allow the normal operation to restore it.

Clock accuracy (DIP module)

DS1553 guarantees the time accuracy of 1 minute per month under +25 degrees Celsius. RTC is calibrated by Dallas Semiconductor Corporation in the factory with non -easy -to -sex tuning elements without additional calibration. Therefore, the clock calibration method is not available and unnecessary. The electrical environment will also affect the clock accuracy, and you should pay attention to put RTC inThe minimum EMI segment of the PC board layout.

Clock accuracy (POWERCAP module)

DS1553 and DS9034PCX for accuracy testing. Once installed together, the module usually keeps the time accuracy within 1.53 minutes (35ppm) per month when +25 C. The electrical environment affects the precision of the clock. Pay attention to the minimum EMI segment of the RTC on the PC board layout.

Frequency test mode

DS1553 frequency test mode uses IRQ/FT output. When the oscillator is running, when the FT bit is 1. The alarm sign (AE) is 0, the door dog control bit (WDS) is 1 or the door dog register reset (register 1ff7h 00h), IRQ/FT Switch at 512Hz. IRQ/FT output and frequency test mode can be used to measure the actual frequency of 32.768kHz RTC oscillator. IRQ/FT pin is an open leak output, which requires a pull -up resistor to work normally. When power is powered, the FT position is cleared to 0.

Use alarm clock

DS1553 alarm setting and control in the register 1ff2H 1ff5h. The register 1FF6H contains two alarm activation bits: alarm enable (AE) and the alarm in the backup enable (ABE). Ae and A BE bits must be set according to the following instructions to activate IRQ/FT output under the matching alarm conditions.

The alarm is programmable to activate at a specific date of one month, or daily, hour, minute or second. It can also be programmed to turn off when the DS1553 is in a battery power supply operation to wake up with a system. Alarm shielding AM1 AM4 control alarm mode. Table 3 shows possible settings. The configuration of the configuration in the table is default per second to inform the user's wrong alarm settings.

When the RTC register value matches the alarm register setting, the alarm logo position (AF) is set to 1. If the alarm logo is also set to 1, the alarm conditions will activate the IRQ/FT pin. IRQ/FT signals are cleared by reading or writing the logo register (address 1ff0h), as shown in Figure 2 and 3. When the CE is activated, the IRQ/FT signal can be cleared by stabilizing the address by 15 ns, or running experience or our validity, but unless the TRC is fulfilled, it cannot be cleared. The alarm logo is also cleared by reading or writing of the logo register, but before the reading/writing cycle and the IRQ/FT signal are cleared, the logo will not change the status.

IRQ/FT pin can also be activated in the battery power supply mode. If ABE and AE are set up and IRQ/FT is set up, IRQ/FT will become lower. During the conversion of power -on conversion, ABE and AE are cleared,However, AF generated during the power off -powering period. Therefore, you can read the AF bit after the system is called to determine whether the alarm is generated during the electric sequence. Figure 4 shows the battery backup mode and the alarm period under power -powered.

Use the door watch dog timer

Watching dog timer can be used to detect out of control processors. Users to program the door dog timer by setting out the timeout time in the 8 -bit door dog register (address 1ff7H). The five -looking dog register position BMB4 BMB0 storage binary multiplication device, two low -order RB1 RB0 selection resolution, of which 00 1/16 seconds, 01 1/4 seconds, 10 1 second and 11 4 seconds. The time of the gate dog is determined by the value of the 5 -bit multiplication device and the 2 -bit resolution value. (For example: Write 00001110 3 x 1 second or 3 seconds in the door dog register.) If the processor does not reset the timer within the specified time period, set the door dog logo (WF) and generate processing processing processing and generate processing processing processing and generate processing processing. The device is interrupted and keeps the activity state until it reads or writes to the door dog logo (WF) or the door dog register (1F7).

The most important position in the door dog register is to see the dog control bit (WDS). When the settings are set to 0, the door dog activates IRQ/FT output when watching the door.

When the WDS is set to 1, the door dog outputs a negative pulse on the RST output, which lasts 40 to 200 milliseconds. When the WDS is set to 1, when the door is over time, the door dog register (1F7) and FT bits are reset to 0.

When the processor executes the reading or writing of the dog register, the door dog timer reset. Then the timeout starts. Write 00h to watch the door dog register will disable the watch dog timer. The door dog function is automatically disabled when power is powered, and the dog register is cleared. If the door dog function is set to the output to IRQ/FT output and the frequency test function is activated, the door dog function is preferred and the frequency test function is rejected.

The default status of the boot

When the device is powered on, the following register position is set to 0:

WDS 0, BMB0 BMB4 0, RB0 RB1 0, AE 0, ABE 0.

Packaging Information

Note: Dallas Semiconductor Corporation recommends the PowerCap module base to use a welded background, the label facing upward (with power defect).

Manual welding and repair: Do not touch or apply the soldering iron to the wire for more than 3 seconds. During welding, apply welded agents on the pad, heating the lead frame pad and welded. To remove the parts, apply the welded agent, the heating lead frame is cushion until the welded reflux, and use the solder core to remove the solder.