Features

* Designed multi-functional monitoring integrated circuit for smart host controllers:

-Provide charging status information for charging batteries

[123 ]-Provide accurate battery voltage and temperature measurement

-Colon charging current points with automatic compensation

* 11-digit digital converter report with reports with the report with the report with the report with the report with Battery voltage with gain and offset correction

* Differential current fluidine

32 byte of universal RAM

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Flash memory of 96 bytes (including 32 -byte shadow flashes)

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8 -byte ID ROM

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Internal temperature sensors do not require external thermal resistance

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Aerable digital input/output port *

High -precision internal current base base Eliminate the external crystal oscillator

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Low power consumption:

-Working: 30 Weian Sleep: 1 Wei'an

] Dormation: 600 mAh

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Single-line HDQ serial interface

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Packaging: 8-lead TSSOP

[ 123]

Explanation

BQ26220 is an advanced battery monitoring equipment, which aims to accurately measure the charging and discharge current of the rechargeable battery pack. BQ26220 aims to integrate battery packs, which contains all necessary functions to form a comprehensive battery capacity management system in portable applications (such as mobile phones, PDAs or other portable products).

BQ26220 cooperates with the host controller in the portable system to achieve the battery management system. The main controller is responsible for explaining the BQ26220 data and transmitting meaningful battery data to the end user or power management system.

The device provides 64-byte of general flash memory, 8-byte ID ROM, and 32-byte Flash-Backed RAM for data storage. Non -loss -loss memory can maintain formatted battery monitor information, identification code, warranty information or other key battery parameters during the temporary short circuit or depth discharge during the battery.

Parameter measurement information

function box diagram

Application information

Functional description

BQ26220 uses voltage-frequency converter measurement of the voltage drop between low-value series fluctuations between SRP and SRN tube feet. The battery voltage is induced between BAT and VSS pin. All data is put into various internal counter and timer registers. Using the information of BQ26220, the system host can determine the charging status of the battery, estimate self -discharge, and calculate the average charging and discharge current. During the packaging and storage, the use of internal temperature sensors doubles the self -discharge counting rate of 25 ° C or more per 10 ° C. Automatically compensate the VFC offset in the charging and discharge counter register.

Through a regulator mapping command protocol, the access and control of the BQ26220 register is achieved through a single -line interface. The protocol includes placing the device in the low -power mode, the reset of the hardware registers, the Flash programming from RAM, and the transmission of Flash data to RAM.

As long as VCC is between 2.8V and 4.5V, BQ26220 can work directly from a single lithium -ion battery.

Charging and discharge meter operation

Table 1 shows the main counter and register of BQ26220.

BQ26220 adds charging and discharge counts to two counter registers, that is, charging count register (CCR) and discharge counting registers (DCR). The charging meter is generated by sensing the voltage difference between SRP and SRN. CCR or DCR counts independently, which depends on the signal between SRP and SRN.

During the discharge process, DCR and discharge time counter (DTC) activation. If (V (SRP (SRN)) is less than 0 (indicating discharge activity), the DCR is counting at a rate equivalent to the rate per 3.05 μVh, and the DTC is counting at 1.138 times per second (4096 times 1 hour). . For example, if the rolling fault diagnostic code register is not started, the negative signal of 24.42 millivoli generates 8,000 DCR counts per hour and 4096 fault diagnostic codes. The power taken from the battery is easy to calculate.)

[ 123] During the charging, CCR and charging time counter (CTC) are in a state of activity. If (V (SRP (SRN)) is greater than 0 (indicating charging), the CCR is counting at a rate equivalent to the rate per 3.05μVh, and the CTC counts at 1.138 times per second. In this case, 24.42 MVs are 24.42 MV. The signal generates 8,000 CCR counts per hour and 4096 CTC counts (assuming no rollover).

DTC and CTC are 16 -bit registers, rolling exceeding FFFFH. If a flip occurs, the corresponding position in the mode register is being being turned out. Settings, the counter increased at 1/256 of the normal rate (16 times per hour).At the same time, the internal RAM and flash memory register of the BQ26220 can be accessed through the HDQ foot.

For self -discharge calculations, the self -discharge count register (SCR) counts at a rate of counting per hour at a rate of one hour at the nominal 25 ° C. The SCR count rate is doubled by about every 10 ° C until 60 ° C. The SCR counting rate is reduced by half of the number of SCR below 25 ° C until 0 ° C. The value in SCR helps to estimate the self -discharge conditions of the battery based on the capacity and storage temperature.

Table 4 shows the BQ26220 register memory mapping. The remaining memory can store users' specific information, such as chemistry, serial number and production date.

Sleep mode operation

BQ26220 responds to the host issued a Sleep command and starts low -power operation. Before entering the low power consumption state, the host processor will write a command to transmit the register to the flash memory. After sending the sleep command and charging and discharge activity less than the value shown in the WOE position shown in Table 2, the chip clock is disconnected, and the data collection function stopped in addition to the self -discharge detection. During the dormant of the device, the BQ26220 cyclical briefly wakes up to maintain a self -discharge register. BQ26220 wakes up the conversion from low to high or from high to low on the HDQ tube feet.

Table 3 shows which registers in normal operation, dormant and dormant period are in active state.

Dormation mode operation When VCC drops below POR threshold V (POR), BQ26220 enters the dormant mode. In this mode, the BQ26220 is absorbed from the RBI pin to keep the RAM data. BQ26220 exit the dormant mode only when the VCC rises to POR threshold.

The current sensing offset calibration and compensation

BQ26220 automatic continuous compensation V (SRP (SRN displacement). No required host calibration or compensation.)

Gas meter control The register

The host maintains the charge and discharge counter (CCR, CTC, DCR, DTC, and SCR). To facilitate maintenance, the BQ26220 CLR register resets a specific counter or register to zero. The host system clears the register by writing the corresponding register bit to 1. When the BQ26220 is reset, the corresponding bit in the CLR register is automatically reset to 0. Clear DTC or CTC registers to clear the mode register STC/STD, and set the CTC/DTC counting rate to the default value of 1.138 times/second.

Equipment temperature measurement

BQ26220 reports the mold temperature of the mold by K by K through the register to TMPH-TMPL. For details, see the TMP register description.

The battery voltage measurement

BQ26220 sensor battery voltage on the battery pins, and report to BATT-BATL through the register. Tank (address 0x72– bit 0 to 2) and BATL low byte register (address 0x71) contain the ADC conversion results on the battery voltage. The voltage is represented by 11 binary formats, and the LSB step is 2.44mv. The Bath's position 2 represents MSB, Batl's bit 0 represents LSB. The measuring voltage of this measurement is 5 V, and the direct sensor in the application of a single battery lithium ion or lithium polarization is optimized (see Figure 3).

Note that the bits of the slot register 3 to 7 storage voltage ADC offset information. The most effective position is the symbol position, which is offset data.

It should also be noted that the LSB gain school (unit is micro -volt) is stored in the complement code of the address 0x79 (byte 1 of ID ROM). The host is responsible for applying the LSB gain factor and offset to ADC measurement.

Correct VBAT VBAT × (2.44+LSB correction factor) -Drived amount

host system and BQ26220 Interchange information through data register interface. See Table 4. The register group consists of 122 position address space, of which 8 -bit bytes are divided into:

8 -byte factories programming ID ROM

32 bytes The shadow of flash memory RAM

64 byte of universal flash memory

18 special function registers

Memory memory

Reading only memory

Location 0x7F to 0x78 contains the LSB gain correction factor containing factory programming ID ROM and voltage modulus converter. The format of the register is shown in Table 5.

Flash shadow RAM

The host system can directly read and modify the 32 -byte RAM. These 32 bytes are shadowed by 32 bytes to provide non -volatile storage of battery status. The information stored in RAM is transmitted to Flash, and the information stored in Flash is transmitted to RAM by writing a single command to the Flash command register (FCMD). When the power -to -time reset occurred, the 0th page of the flash memory was transmitted to RAM. For more details, see the Flash command register part.

User flash memory

In addition to the flash memory shadow RAM, BQ26220 also has 64 -byte user flash memory. User flash memory can store specific battery pack parameters, such as charging by VFC pulse, batteryizationLearning and spontaneous electricity.

Flash Programming

The two sets of direct user flash memory of one byte, but a single set of flashing shadows can be programmed at one page, or the transmission code of RAM to flash memory is written into the flash command register register (FCMD). This programming is performed by writing the required code into the flash memory command register FCMD (address 0x62). The host can transmit data between the flash memory and RAM. For more details, see the Flash command register part. The summary of the Flash command code is shown in Table 6.

single byte programming

To program a single byte in Flash, first write the data byte to the FPD register, and write the address of the programming address. Enter the FPA register. The programming command 0x0f is then written into FCMD. As a result of this sequence, the content of the FPD register is logically and operational with the content of the Flash address pointed by the FPA register.

RAM to flash memory transmission

When sending RAM to the Flash transmission command, logically corresponds to RAM content is the hidden user RAM Flash content. If you want to write new data on the old data, you must first erase the flash memory pages that are being updated and restore all the necessary data.

Communication with BQ26220

BQ26220 includes a single -line HDQ serial data interface. The host processor is configured as rotation or interrupt processing, and uses the interface to access various BQ26220 registers. The HDQ pin requires an external pull -up resistor. The interface uses a command -based protocol, where the host processor sends the command by byte to the BQ26220. The command instructions BQ26220 store the receiving eight -digit data to the register specified by the command byte, or output eight -digit data from the register specified by the command byte.

The communication protocol is returned asynchronous and referenced to VSS. The command and data byte consist of 8 -bit flow, and its maximum transmission rate is 5 kbits/s. The minimum effective bit of the command or data byte is first transmitted. The data entered from the BQ26220 can use the pulse width available on the microcontroller to capture the fixed timer for sampling. UART (General asynchronous Receive launcher) also communicates with BQ26220.

If the communication timeout occurs (for example, if the host wait time exceeds T (CYCB waiting for BQ26220 response or if this is the first access command), the host should send an interrupt. Then, the host can send the command. When the HDQ tube foot is driven to the low state of the logic reaches T (B) or a longer period of time, the BQ26220 detects disconnect. Then the HDQ tube foot returns to the normal high level logic state within a period of time (Bill. Then, then, BQ26220 PrepareReceive commands from the host processor. )

Return a data bit frame consists of three different parts:

1. The first part is transmitted by the host or BQ26220, so that HDQ PIN is equal to T (HW1) or T (DW11111 or DW11 ) During the period, it is in a logical low state.

2. The next part is the actual data transmission. After the negative edge of the communication, the validity period of the data should be equal to T (HW1) or T (DW1). The data should be preserved as T (HW0) and T (DW0) that allows hosts or BQ26220 to sampling data bits.

3. The last part can stop transmission by returning HDQ PIN at least T (DW0) or T (HW0) after the negative edge used to start communication. The final logic high level state should be maintained to the cycle of T (Cych) or T (Cycb) in order to ensure that the bit transmission stops correctly.

The timing specifications and diagram parts of serial communication are given data and interrupt communication timing. Communication with BQ26220 always occurs when the minimum effective position is sent first. Figure 4 shows an example of the communication sequence of the BQ26220 DCRH register.

The command byte

The command by byte of the BQ26220 consists of eight continuous effective command positions. The command bytes contain two fields: W/R COMMAND and Address. The W/R bit of the command register determines whether the command is read or write the command, and the address field containing the address of AD6-AD0 indicates the address to be read or write. The command byte value is shown in Table 7.

BQ26220 register

register maintenance

The host system is responsible for registration and maintenance. (See Table 4.) In order to facilitate maintenance, BQ26220 Clear the register (CLR) to reset the specific counter or register to zero. The host system clears the register by writing the corresponding register bit to 1. When the BQ26220 is reset, the corresponding bit in the CLR register is automatically reset to 0, so as to save an additional writing/reading cycle for the host. Clear the malfunction of the criteria to remove the standard bit and set the default diagnostic code count to the default value of a counting per 0.8789 seconds. Clear CTC register will remove the STC bit and set the CTC counting rate to the default value of a counting per count of 0.8789 seconds.

The register description

The battery voltage offset register (slot)

The bit of the storage voltage ADC of the storage voltage ADC of the storage voltage ADC of the storage voltage ADC. The most effective position is the symbol position, which is offset data. Each count of offset represents 8 MV. The host is responsible for being reduced from the unrefined values found in the Bath and BATL registersTo measure the offset. This is a symbol quantity value, and the bit 7 is the symbol. 1 in bit 7 indicates that numbers are negative.

Battery voltage register (BATH/BATL)

slot (address 0x72 -bit 0 to 2) and BATL low byte register (address 0x71) containing the ADC conversion result on the battery voltage Essence The voltage is represented by 11 binary formats, and the LSB step is 2.44mv. Bath's position 3 indicates MSB, Batl's bit 0 means lsb.

Flash memory program address register (FPA)

FPA byte register (address 0x70) points to the flash memory address of the programming command when it sends out. This byte, together with FPD and FCMD registers, is used to program a single byte in flash memory.

The storage program data register (FPD)

FPD byte register (address 0x6f) contains data from the flash memory address positioning to the contents of the FPA register content. When the Flash command is issued, the content of the FPD register is added to the contents of the bytes of FPA, and then stored to the location.

discharge counting register (DCRH/DCRL)

DCRH high byte register (address 0x6e) and DCRL low byte register (address 0x6d) contain discharge counts, when V LT; V These registers continue to count when counting more than FFFFH, so the host system needs correct register maintenance. CLR registers forced DCRH and DCRL to zero.

charge counting register (CCRH/CCRL)

CCRH high byte register (address 0x6c) and CCRL low byte register (address 0x6b) contains charge counts, and Time increase. The count of these registers continues to exceed FFFFH, so the host system should perform appropriate register maintenance. CLR registers forced CCRH and CCRL to zero.

Self -discharge counting register (SCRH/SCRL)

SCRH high byte register (address 0x6a) and SCRL low byte register (address 0x69) contain self -discharge counts. The register is continuously updated under the normal working mode and dormant mode of BQ26220. The counts in these registers increase according to time and temperature. At 20 ° C to 30 ° C, SCR counts at a rate of one hour per hour. At the temperature above 60 ° C, the counting rate doubles every 10 ° C, up to 16 times/hour. At a temperature below 0 ° C, the count rate is reduced by half of ° C to 30 ° C, and the minimum is 1/8 hours. These registers continue to count after FFFFH, so the host system should properly maintain the register. Clr sendThe depositor is forced to reset the SCRH and SCRL to zero. During the dormant of the device, the BQ26220 cyclically awakened for a short period of time to maintain a self -discharge register.

discharge time counting register (dtch/dtcl)

DTCH high byte register (address 0x68) and DTCL low byte register (address 0x67) determine V LT; v means the discharge time length. The count in these registers increasing at 4096 counts per hour. If the DTCH/DTCL register continues to count more than FFFFH, the STD bit is set in the Mode/WOE register to indicate the flip. Once settings, DTCH and DTCL increased at a rate of 16 counts per hour.

Note: If the second rolling occurs, the STD is cleared. The time to visit BQ26220 should be cleared by DTCH/DTCL every 170 days. The CLR register forced DTCH and DTCL to zero.

Charging time count register (CTCH/CTCL)

CTCH high byte register (address 0x66) and CTCL low byte register (address 0x65) to determine the length of the v gt; V. Indicates charging activities. The count in these registers increasing at 4096 counts per hour. If the CTCH/CTCL register continues to count more than the FFFFH, the STC bit is set in the Mode/Woe register that indicates the flip. Once settings, DTCH and DTCL increased at a rate of 16 counts per hour.

Note: If the second rolling occurs, the STC is cleared. The time to visit BQ26220 should be cleared by CTCH/CTCL every 170 days. CLR registers forced CTCH and CTCL to zero.

mode register (mode)

Mode register (address 0x64) includes GPIEN, STA, STD, POR, and Awakening information, as shown in Table 9.

Clear the register (CLR)

CLR register (Address 0x63) to clear DCR, CCR, SCR, DTC, and CTC registers, through forced compulsory upper topics Electricity and settings are reset to BQ26220 as described in Table 11.

Flash instruction register (FCMD)

FCMD register (Address 0x62) is the Flash command register for programming a single Flash byte position, executing the Flash page Remove, transmit RAM to Flash and Flash to RAM, enter sleep mode and shut down. These functions are sent by writing the required command code to FCMDThe depositor is executed.After completing the execution commands of the BQ26220, the Flash command register is cleared.

Templim register (TMPH, TMPL)

TMPH (address 0x61) and TMPL register (address 0x60)Unit reported mold temperature.All 8 -bit and TMPH registers of TMPL low registers are reported to 11 digits of the temperature.The temperature should be read to TMPH [2: 0] and TMPL [7: 0], 0.25K/LSB.TMPH's 5 MSBS, TMPH [7: 3] is cleared and retained on the POR.When reading temperature, 5 bits should also be blocked to ensure that incorrect data is not used when calculating the temperature.

Packaging material information