Features

* Single CMOS A/D converter

- Micro -processor compatibility

- Parallel and serial output [123 ]

- Inherent tracking/Keep input

* Zhen 12, 14 and 16 -bit accuracy

*

conversion time [123 ] - CS5016

: 16.25 microseconds

- CS5014

: 14.25 microseconds

- cs5012a : 7.200 μs

* Linear error: ± 0.001%fs

- Guaranteed no loss code

*

Self -calibration to maintain accuracy [ 123]

- Precise change over time and temperature

*

Low power consumption

- 150 MW

*

*

] Low distortion

Note CS5012A/14/16 is 12-bit, 14-bit, and 16-bit single simulation-digital converter, the conversion time is 7.2 microseconds, 14.25 microseconds, and 16.25 Micros. The unique self -calibrated circuit ensures good linearity and differential non -linear, without leakage. The offset and full standard error remained in 1/2 LSB (CS5012A/14) and 1 LSB (CS5016), and no calibration was required. A single and bipolar input range can be selected.

The CS5012A/14/16 compatible with the pin is composed of DAC, conversion and calibration microcontroller, oscillator, comparator, microprocessor compatible three -state I/O and calibration circuits. The input tracking of the inherent inherent in the device sampling structure is converted to the use of a fast -rotated inner buffer AM Plifier. This allows throughput of up to 100 KSPS (CS5012A), 56 KSPS (CS5014) and 50 KSPS (CS5016).

Operation theory

CS5012A/14/16 series adopts one time approximation of conversion technology. Simulation input and D/A converter controlled by the conversion algorithm. The approximation of the one -time simulation input and DAC output is set to half -scale (MSB is open, all other places are off). If the input is found to be less than half a scale, the MSB is reset to zero, and the input is changed to a quarter of the degree (the next MSB is opened, and all other MSBs are closed). If the input is higher than the semi -standard, the highest effective bit will be maintainedAt the high position, the next comparator will be at three quarters of the standard. This process will continue until all places are executed.

A unique charge re -assignment structure is adopted to achieve approaching algorithm one by one. DAC is not a traditional resistance network, but a set of binary weighted capacitors. All the capacitors in the array share a public node at the input end of the comparator. Their other terminals can be connected to Ain, Agnd or VREF (Figure 1). When the device is not calibrated or converted, all capacitors are related to Ain that forms CTOT. The switch S1 is turned off, and the charge on the array qin tracks the input signal vin (Figure 2A).

When a conversion command is issued, the switch S1 is opened, as shown in Figure 2B. This trap is charged to qin on the comparator side of the CAPACI TOR arrays and creates a floating node at the input end of the comparator. The conversion algorithm operation on this fixed charge ignores the signal of an analog input pin. In fact, the entire DAC capacitance array acts as analog memory during the conversion, just like sampling/maintaining the capacitor in the amplifier.

This conversion includes the free board of the capacitor array converted into VREF and agng to form a capacitor pressure device. Due to the unchanged charging of floating point, the voltage of this point depends on the proportion of capacitors connected to VREF and agng. The proportion of capacitors is used to approach the algorithm one by one. As shown in Figure 2B, when the capacitor is connected to the reference voltage, the voltage at the driving floating node (VFN) is zero. The binary part of the capacitor represents the digital output of the converter.

This charged re -distribution structure is easy to support the bipolar input range. If half of the capacitor array (MSB capacitor) is bound to VREF instead of AIN in tracking mode, the input range doubles and offset half -scale. Therefore, the size of the reference voltage defines the positive standard and negative standard (-VREF to+VREF), and the digital code is the binary representation of the input.

Calibration

CS5012A/14/16 whether it can accurately change, which obviously depends on the accuracy of its comparator and DAC. CS5012A/14/16 uses the automatic zero " solution to eliminate the error of the comparator's introduction. When you are in the tracking mode