Modification of LTB gain (optional)

Internal gains can be modified through SS/LTBG/AMD pins, as shown in Figure 13. SS/LTBG/AMD pins are also used to set up soft startup time, so the SS/LTBG/AMD pin must be modified after the soft start is completed. Use the D diode and R3 resistor (the red block in Figure 13). After the soft start, the current from SS/LTBG/AMD pins to SGND is zero, so the internal gain is not modified. AS result LTB gain is the default value (LTB gain u003d 2). In order to reduce the LTB gain, a square of circuit graph 13 consisting of Q, R1 and R2 (blue) must be used. ) After the soft start, the current from SS/LTBG/AMD pins only depends on the R1 resistor, so reducing the R1 resistance value can reduce the LTB gain. The sum of R1 and R2 must be selected to obtain the required soft start time.

Dynamic video conversion

This device can manage dynamic video encoding of the output voltage changes during the normal operation period of the device. OVP and UVP signals (and AMD modes) are blocked during each VID conversion period, and the conversion will be converted at 32 clock cycles to prevent transition from transition. When dynamically changing the regulatory voltage (D-VID), the system needs to charging or discharge the output capacitance accordingly. This means that an additional ID-VID needs to be considered when an over-current threshold must be set when the output voltage is increased. You can use the following relationship:

For DV LS6, select VRDAC output or VRDAC to 25 millival 25 millivol (for AMD DAC) and TVID between each LSB conversion Time interval (external driver). The overcoming OC threshold during dynamic video will cause the device to enter the constant current limit to slow down the output voltage DV/DT, which also causes the fault to be in the D-VID test. L6713A check the VID code modification of the internal rising edge (see Figure 14) an additional DVID clock, wait for the confirmation of the lower edge. Once the new code is stable, in the next rising edge, the reference begins to rise or falls to LSB to increase the per VID clock cycle until it reaches the new VID code. During the transition, the VID code change was ignored; after the device was re -monitoring, VID was restarted to monitor VID to complete the next rising edge. Frequency (VID) depends on the working mode of the clock selection: For Intel mode, it is within 1MHz to ensure compatibility and specifications. At the same time as the AMD mode, this frequency is reduced to about 250kHz. When the L6713A executes D-VID conversion in AMD mode, the DVID pin is pulled up, as long as the device is being executed (including additional 32 clock delay)

Enable and disable

L6713A has three different power supplies: providing VCC pins for internal control logic, VCCDRX provides low -end drivers, and BOOTX provides high -end drivers. If the voltage is not higher than the connection threshold specified in the electrical specifications in the pins VCC and VCCDRX, the device is closed: the MOSFET displayed high load impedance of all the drives is closed. Once the device is supplied correctly, it can ensure that the device can be driven by OUTEN pipe to control the time sequence of the power supply. Set up without a pin, and the device realizes soft start -programming voltage. Short pins to SGND, and reset device (in this case, SS_END/PGOOD on SGND short circuit) from any lock state, it also prohibits the device that keeps all MOSFET rotation.

Soft start

L6713A realized soft startup to charge the output filter smoothly to avoid the current of the peak input power supply. The device increases the operation according to the selected operation, and increases zero -to -programming value mode and output voltage in different ways. Only when all power supply is higher than its own opening threshold and the external pins are released can the device be soft startup. At the end of the number soft start, the SS_END/PGOOD signal was released. The protection measures are activated at this stage; when the reference voltage reaches 0.6V, the lack of voltage is enabled and the overvoltage always depends on the threshold enable mode of the selected operation or the fixed threshold programming by ROVP (see ""overvoltage and programmable programming can be programmable and programmable OVP ""part).

Intel Mode

Once L6713A receives all the correct power supply and enables it, and after the Intel mode selection, the soft start -up stage is launched. The delay is T1 u003d T1 u003d 1ms (min). After that, the references rose to VBOOT u003d 1.081V (1.100V-19MV) and wait for T3 u003d 75 μSEC (typical values) in T2 according to SS/LTBG/AMD settings. The output voltage will then rise to the programming value in T4 with the same slope (see Figure 15).

SS/LTB/AMD defines the main oscillator used to jump from zero to programming; this oscillator is independent of the frequency of programming through OSC pins. In particular, it allows accurate programming startup time to VBOOT (T2) because it is a fixed voltage independent of a programmable video display. The total soft launch time depends on the VID results of programming (see Figure 17 and Figure 19).

The protection is effective during soft start. After the reference voltage reaches 0.6V, UVP is enabled and before VBoot, OVP always activate the VID (or programming VOVP) with a fixed 1.24V threshold and threshold (see) after VID (or programming VOVP) (see The red dotted line chart 15).

Note: If the VID of programming during T3 selects the output voltage below VBOOT, the output starts from VBOOT, and the voltage will rise to the programming voltage.

SS/LTB/AMD connection SS/LTB/AMD pins at the time of LTB gain u003d 2 is connected to the ssend/pgood pins through the signal diode (see Figure 16) according to the resistance RSSOSC.

Among them, TSS is to reach the time of programming voltage VSS and RSSOSC. ;.

Use the SS/LTB/AMD connection of the LTB gain ltb; 2 o'clock when using the LTB gain lt; Before the soft start was not completed, the Q crystal tube was turned off (see Figure 18).

Among them, TSS is connected between SS/LTBG/AMD and SGND (RSSOSC u003d R1+R2), which is the time spent on the programming voltage VSS and RSSOSC. The unit is K #8486;.

AMD mode

Once the L6713A receives all the correct power supply and enables it. After the AMD mode is selected, it will enter the benchmark from zero to programming value by zero step to programming value. Let's start the soft start VID code (see Figure 15); the clock that is now used for the reference as the main clock is the same as the OSC pin programming, and the SSOSC pin is not applicable in this case. Then, the soft start time results (see Figure 20):

Among them, TSS is the time that VSS is spent, FSW is the main switching frequency programming by OSC pin. The protection activation during the soft start is 0.6V during the reference voltage, and OVP is always in a fixed 1.800V threshold (or programming VOVP).

Low -side activation

In order to avoid any type of negative rushing in the load side during the startup process, L6713A executes a special special when the LS drive can be switched when switching Sequence: Disable the results of the LS driver during the soft start -up phase (ls u003d closed) until HS starts switching. This can avoid the negative peaks on the risk output voltage, if it starts on the pre -definition output (see Figure 21). This special feature of the device blocks only from the point of view: If the voltage occurs, the need to protect the LS MOSFET still allows it.

output voltage monitor and protection

L6713A monitor the voltage by monitoring the voltage by pins, and manages OVP, UVP, and good (applicable) conditions. When programming different operation modes (Intel or AMD, see Table 11), the response to the protection event is still the same as described below. When using the offset function, OVP, UVP, and PGOOD thresholds according to the offset voltage: during the soft start (see the ""soft start"" section), in the case of shielding, the protection is also in the active state during the D-VID conversion period. After the conversion, there is an additional 32 -clock cycle delay to avoid errors.

Implit voltage

If the output voltage monitored by VSEN is lower than the programming value of -750mV or more, for more than one clock cycle, L6713A closed all MOSFETs and locking conditions: To recover, you need to circulate VCC or need to circulate VCC or need OUTEN pin. This is independent of the choice operation mode.

Preliminary overvoltage

When VCC is lower than the UVLOVCC threshold, it provides protection. CPU is damaged when the HS MOSFET failure must be avoided. In fact, because the device is the 12V bus, it is basically ""blind"" for any voltage below the opening threshold (UVLOVCC). In order to provide comprehensive protection for loads, preliminary OVP protection is provided in LovuVCC when VCC. As long as the VSEN tube foot voltage is greater, this protection will turn on the low -side MOSFET greater than 1.800V, lag 350mv. After setting, the voltage from the LS MOSFET door to the source of the driver depends on the opening threshold (UVLOVCCDR) applied by the voltage applied on VCCDRX through these pins. This protection also depends on the status of the outen tube. When the device is closed, a simple method of protecting the output in all cases (then avoid the non -protected red area on the left side of Figure 22) includes the provision of the controller through the 5VSB bus, as shown in Figure 22 on the right: 5VSB before the 5VSB. The+12V that always exists. In the case of HS short circuit, LS MOSFET is driven by 5V to ensure reliable load protection. For Intel and AMD mode.

Over -voltage and programmable OVP

Once the VCC exceeds the opening threshold and the device is enabled (outen u003d 1), L6713A provides overvoltage protection: when VSEN induction should be induced, The voltage to overcome the OVP threshold, the controller permanently opens all low -end MOSFETs and close all high -sides MOSFET to protect the load. OSC/fault pins drive voltage (5V) and require a power or external pin cycle to re -start the OVP threshold to change according to the selected operating mode (see Table 11). OVP threshold can also be programmed through OVP pin: let the pin float, it is pulled up inside, and the OVP threshold is set according to Table 11. Connect OVP pins to SGND through the resistor ROVP, and the OVP threshold becomes the existence voltage at the large head needle. Because the OVP pin provides a constant IOVP u003d 12.5μA current (see Table 4), the programming voltage becomes:

Maximum (100pf) and maximum value.

PGOOD (only applicable to AMD mode)

It is an open leaky signal released after the soft startup program is completed. It was pulled down when the output voltage was lower than the -300MV that is lower than the programming voltage.

The integrated large current driver allows the use of different types of power MOS (can also reduce equivalent RDSON) to keep the fast switch conversion. The driver of the high -voltage side MOSFET uses the Bootx pin to supply power, and the Phasex pin is used to return. The low -end MOSFET driver uses VCDRX pins as a power supply and PGNDX pin for reward. The minimum voltage on the VCCDRX pin requires the device to start running. VCCDRX needle must be connected together. This controller contains a complex reflex system to minimize the transmission time of the low -oriented diode to maintain good efficiency and save the use of the Schottky diode: when the high -voltage side MOSFET is closed, the voltage on its source starts to decrease; when the voltage reaches reaches At 2V, the low -voltage side MOSFET gate driver suddenly applied. When the low side MOSFET is closed, the voltage on the LGATEX pin is detected. When the voltage drops to less than 1V, the high -voltage side MOSFET gate driver is suddenly applied. If the current in the inductors is negative, the source of the high side MOSFET will never be let go. Even in this case, the low -side MOSFET is allowed to open it, and a watch dog controller is enabled: If the source of the high side MOSFET does not decrease, the low side MOSFET is opened, which allows the negative current of the sensor to re -cycle. Even if the current is negative, the mechanical device can regulate the system. CDRX and VCIC pins are also separated from the power pins signal (SGND pins) and power grounding (PGNDX pins) in order to maximize switching and resistance. Independent power supply of different drivers is highly flexible. When selecting MOSFET, it allows the use of logic level MOSFET. Several supply combinations can choose to optimize the performance and efficiency of the application. Power conversion input is also flexible; 5V, 12V bus or any allowable conversion bus (see maximum duty cycle limit) can be freely selected.

System control circuit compensation

The control circuit's measog control loop (see Figure 9) The average current mode control loop. In the case of appropriate gain, each loop will minimize the PWM regulating error: the average current control loop should be controlled by the average current mode control loop fixed output voltage equal to the reference value of VID programming. FIG. 25 shows the system control circuit diagram. The system control loop is shown in Figure 26. The current provided by idroopThe information flows into RFB through the foot of the descending pipe to achieve a dependent reading current on the output voltage.

This system can use an equivalent single phase transformer to build an equivalent induction sensor L/N (one of each of which has a L power sensor) ring circuit The result of gain (open the ring road after compensation pins):

When embedded in virtual reality based on L6713A

embedding VRD into the application, it must be careful, because the entire VRD is the entire VRD is A switch -type DC/DC regulator is also the most common system work is a digital system, such as MB or similar. In fact, the latest MB has become faster and functional: high -speed data bus is becoming more and more common and switching noise. If it does not follow other layout guidelines, the data generated by VRD may affect data integrity. When the route high exchange path, it is necessary to consider several easy point currents (high -switching current will cause the trajectory of the noise of the nearby records on the voltage of the mixed inductance): Keep the large current switch VRD trajectory and data bus of the large current switch and the data bus of the data bus) Safety protection distance, especially high -speed data bus, minimize noise coupling. When tracking the I/O subsystem routing deviation, keeping a safe protection distance or appropriate filtering must be walked near the VRD. The possible cause of noise can be positioned in the phase connection, the MOSFET gate driver and the input voltage path (from the input large -capacity capacitor and HS drain). There are also PGND connections. If you do not insist on using the power ground plane, you must consider it. These connections must be careful of the data bus that is sensitive to noise. Because the noise generated is mainly due to the switching activity of the VRM, the noise emissions depends on the speed of the current conversion. In order to reduce the level of noise emissions, in addition to the previous guidelines, it can also appropriately reduce the current sloping HS door resistance and phase buffer network.