Features

2: 4 Differential buffer

Enter to receive LVPECL, LVDS and LVCMOS/LVTTL

Four LVPECL output

Maximum clock frequency: 2 gHz

maximum Iron core current consumption: 45 mia

very low additional jitter: lt; 100 fs, 10 kHz to 20 MHz offset range:

–57 FS , RMS (typical values) under 122.88 MHz

- 48 FS at 156.25 MHH, RMS (typical value)

–312.5 trillion at 30 fs, RMS (typical value) [typical value) [typical value) [typical value) [typical value) [typical value) [typical value) 123]

2.375-V to 3.6-V device power supply

Maximum communication delay: 450 PS

maximum output deviation: 15 PS

LVPECL reference voltage, VAC_REF, can be used for capacitive coupling input

Industrial temperature range: –40 ° C to+85 ° C

Support 105 ° C PCB temperature (measurement at the hot pad)

ESD protection exceeds 2 kV (HBM)

#8226; Wireless Communication

Telecom/Network

Medical imaging

testing and measurement equipment

Explanation

CDCLVP1204

is a multi -purpose, low -additional hibirus cusher, which can generate four LVPECL clock output copies from two optional LVPECL, LVDS or LVCMOS inputs. Used for various communication applications. Its maximum clock frequency is as high as 2 Giggle. CDCLVP1204 has a multi -road reuse (MUX) on one piece, which is used to select one of the two inputs. These two inputs can easily control the terminal configuration alone. The overall jitter performance is less than 0.1Ps, and the all -rooted root is from 10kHz to 20MHz. The overall output deviation is as low as 15PS, making the device a perfect choice for high requirements for applications.

CDCLVP1204 clock buffer to input two optional clocks (in in0, IN1) is allocated to the four -pair of differential LVPECL clock outputs (OUT0, OUT3). CDCLVP1204 can receive two clock sources into the input multi -way relics. The input can be LVPECL, LVDS or LVCMOS/LVTTL.

CDCLVP1204 is designed for driving 50Ω transmission lines. When the input is driven by a single-end mode, the LVPECL bias voltage (VAC_-Ref) must be applied to the unused negative input terminal. However, for high -speed performance up to 2GHz, it is strongly recommended to use differential mode.

CDCLVP1204 is characterized by working between -40 ° C and+85 ° C.

Preface Figure

(1) The calculation method of the output deviation is as follows: Most Most: Most Most: The difference between fast and slower TPHLN (n 0, 1, 2 .... 11), or the difference between the fastest and slowest TPHLN (n 0, 1,2 .... 11). (2), some of the computing results of part of the inclined inclination are as follows: the difference between the fastest and slower TPHLN (n 0, 1,2 .... 11) on multiple devices, or in The difference between the fastest and slower TPHLN (n 0, 1,2 .... 11) on multiple devices.

Typical features TA --40 ° C to+85 ° C (unless there are other instructions).

Parameter measurement information

Test configuration

Figure 5 to 11 illustrates how to make various tests for each block of CDCLVP1204 Configure the setting device.

Test configuration

Detailed description

Overview

CDCLVP1204 is an open transmitter output by LVPECL. Therefore, proper bias and terminals need to be appropriately operated to ensure the correct operation of the device and minimize signal integrity. The correct end of the LVPECL output is 50Ω to (VCC – 2) V, but the DC voltage is not easy to obtain on the PCB. To this end, this article designs a LVPECL terminal Davidan equivalent circuit with two structures of direct coupling and coupled. These configurations are shown in Figure 12 (A and B) (VCC 2.5V) and Figure 13 (A and B) (VCC 3.3V). It is recommended to close all resistor elements close to the drive side or receiver end. If the power supply voltage of the driver and the receiver is different, it needs to be coupled.

Figure Figure

SpecialThe description

CDCLVP1204 is a low -added jitter, which is commonly used to have two optional LVPECL fan out buffers. Small packaging, low output bias, and low additional jitter make the device very flexible in demanding applications.

Equipment function mode

The two inputs of CDCLVP1204 are mixed internally, which can be selected by controlling the pin. Unused input and output can keep floating to reduce the cost of overall components. AC and DC coupling schemes can be used with CDCLVP1204 to provide greater system flexibility.

LVPECL output terminal connection

Input terminal connection

CDCLVP1204 input can be as LVPECL, LVDS Or LVCMOS driver interface. FIG. 14 illustrates how to couple DC LVCMOS into CDCLVP1204. The series resistance (RS) must be close to the LVCMOS driver; its value is calculated based on the difference between the transmission line impedance and the driver's output impedance.

FIG. 15 shows how to input LVDS input with CDCLVP1204. Figure 16 and 17 describe the method of coupled LVPECL input to CDCLVP1204 when VCC 2.5V and VCC 3.3V, respectively.

FIG. 18 and 19 Display VCC 2.5V and VCC 3.3V, and the AC coupling input technology of CDCLVP1204 shows. It is recommended to close all resistor elements close to the drive side or receiver end. If the power supply voltage of the driver and the receiver is different, it needs to be coupled.

Application and implementation

Note: The information in the following application parts is not part of the TI component specification, TI does not guarantee its accuracy or integrity Essence TI's customers are responsible for determining whether the part is suitable for its purpose. Customers should verify and test their design implementation to confirm the system function.

Application information

CDCLVP1204 is a low -added lvpecl fan buffer, which can generate two copies of two optional LVPECL, LVDS or LVCMOS inputs. CDCLVP1204 can accept a reference clock frequency of up to 2GHz, while providing low output deviations.

Typical application

line card application fan -shaped output buffer

Typical application (continued)

Design requirements [ 123]

Figure 20The CDCLVP1204 shown is configured to choose two inputs, a 156.25 trillion LVPECL clock from the back panel, or a secondary 156.25 trillion LVCMOS 2.5 volt oscillator. As shown in the figure, any signal can be scattered to the required device.

Configuration example Drives 4 LVPECL receivers in a wire card application with the following attributes:

PHY device has internal communication coupling and appropriate terminal and bias. CDCLVP1204 needs to be equipped with a 86Ω launch resistance near the drive to ensure normal work.

ASIC can perform DC coupling with the 2.5 V LVPECL driver (such as CDCLVP1204). The ASIC has an internal terminal, so there is no additional component.

FPGA requires external communication coupling, but there is an internal terminal. Similarly, 86Ω launch polar resistors are placed near CDCLVP1204, and 0.1 μF is placed to provide AC coupling. Similarly, the CPU internal end is connected to an external AC coupling capacitor.

Detailed design program

For the correct input terminal connection, please refer to the input terminal connection, which depends on a single -end or differential input.

For the output termination plan of the receiver application, please refer to the LVPECL output termination.

Unused outputs can be kept floating.

In this example, PHY, ASIC, and FPGA/CPU need different solutions. Power filtering and bypass are the key to low noise applications.

Recommended filtering techniques, please refer to the power suggestion. A reference layout is provided on the CDCLVP1204 evaluation module of SCAU032.

Application curve

low additional noise of CDCLVP12XX can be displayed in this line card application. There is a low noise of 32 FS RMS jitter 156.25 MHz XO driving CDCLVP12XX. When integrated from 10 KHz to 20 MHz, 57 FS RMS is generated. The surcharge generated by this is a low 47 FS RMS.

Power recommendation

High -performance clock buffer is sensitive to noise on the power supply, which will significantly increase the additional jitter of the buffer. Therefore, the noise from the system's power supply must be reduced, especially when the jitter/phase noise is critical to the application.

Filter capacitors are used to eliminate low -frequency noise of power supply. Among them, bypass electrical containers provide extremely low impedance paths for high -frequency noise and protect the power system from inductive fluctuations. These bypass capacitors also provide instantaneous currents required by the device.Has low -equate series resistance (ESR). In order to correctly use the bypass container, they must be placed in a place very close to the power supply terminal and arranged with a short circuit to minimize the inductance. It is recommended to add as many high frequencies (for example, 0.1-μF) bypass containers as possible because there is a power terminal in the package. It is recommended (but not necessary) to insert iron oxygen magnetic beads between the board power supply and the chip power supply to leave the high -frequency switching noise generated by the isolated clock driver; these magnetic beads can prevent the switching noise leak into the board power supply. The appropriate iron oxygen magnetic beads with extremely low DC resistance must be selected in order to provide sufficient isolation between the circuit board power supply and the chip power supply, and keep the voltage at the power terminal higher than the minimum voltage required for normal work.

FIG. 23 illustrates the recommended power decoupling method.

Layout

Layout Guide

The power consumption of CDCLVP1204 may be high, and it is necessary to pay attention to thermal management. For reliability and performance, the mold temperature must be limited to up to 125 ° C. In other words, it is estimated that the ambient temperature (TA) plus equipment power consumption must not exceed 125 ° C with Rθ.

The device encapsulates an exposed pad that provides the main heat dissipation path to the printing circuit board (PCB). In order to maximize the heat dissipation, a hot landing mode, including multiple pores of a ground plane, must be included in the footprint of the encapsulation in the circuit board. The exposed pads must be welded to ensure that there is enough thermal conductivity outside the packaging. Figure 24 shows the recommended LAND and VIA models.

layout example

Thermal factors

CDCLVP1204 support the high temperature on the printed circuit board (PCB) measured at the hot pad. The system design needs to ensure that it does not exceed the maximum connection temperature.人员JB allows the system designer to use the regular thermocouple measuring board temperature and use equation 1 to linked knot temperature. Note that 近JB is close to Rθ, because 75%to 95%of equipment calories are distributed from PCB. For more information, please visit SPRA953 and SLUA566.

Example:

Use the four -layer jedec test board with four heating holes to calculate the connection wire temperature:

[ 123]

Power Inclterm IMAX × V Max 186MA × 3.6V 669.6MW (including the maximum power consumption including terminal resistance)

PowerExClterm 518.6MW (excluding the maximum power consumption of the terminal resistance For details, see Slyt127)

Δt knot ψjb × PowerexClterm 19 ° C/W × 518.6MW 9.85 ° C.assis 9.85 ° C+105 ° C 114.85 ° C (does not violate the highest knot temperature of 125 ° C)

Packaging material information

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