Features

* 1MHz frequency ability

* fixed frequency voltage mode operation, feedback

Hot shutdown

Low -voltage lock

Precise programming maximum duty cycle limit [

123]* 1A receiver/source grid drive

* Able -programming pulse cross -current protection

Aterior edge current current Sensing Condition

75NS shutdown and transmission delay

Able to soft start

Low -voltage protection

Able -looking lag overvoltage protection

* 25ns Rising and decreased time (1NF load)

3.3V 3%reference voltage output Instructions

The PWM controller of the pre -frequency feed voltage mode contains all the functions required for the basic voltage mode operation. The PWM controller has been optimized to high -frequency main control operation. In addition, the device also has the following characteristics: soft startup, ACCU Rate duty cycle limit control, start -up current less than 50 microan, exceeding low -pressure protection, two -way synchronization. CS51221 has 16 -line PDIP and narrow surface installation packages.

Application Relationship Figure

36V-72V to 5V/5A converter

Operation theory

Feming voltage mode Control

In the traditional voltage mode control, the slope signal has a fixed rise and decrease slope. The feedback signal is only guided by the output voltage. Therefore, the voltage mode control has lower line adjustment and audio sensitivity.

The feed voltage mode control exports the slope signal from the input cable, as shown in Figure 1. Therefore, the slope of the slope changes with the input voltage. At the beginning of each switch cycle, a capacitor connected to the FF pin is charged by the resistor connected to the input voltage. At the same time, the gate output is turned on to drive the external power switch device. When the FF pin voltageWhen the error amplifier outputs VCOMP, the PWM comparator turns off the gate, and the gate is turned on to open the external switch. At the same time, the FF capacitor is quickly discharged to 0.3V.

In general, the dynamic characteristics of the duty cycle are controlled by the input and output voltage. As shown in Figure 2, under a fixed input voltage, the output voltage is adjusted by an error amplifier. For example, increased output voltage will reduce VCOMP, which will lead to a decrease in the duty cycle. However, if the input voltage changes, the slope of the slope signal will immediately respond, thereby providing a great improvement line transient response. As shown in Figure 3, when the input voltage rises, the increase of the slope signal increases, thereby reducing the working cycle to offset the change.

The feeding feature can also be used to provide olty seconds clamping, thereby limiting the input voltage and the maximum product of the opening time. This clamper is used in circuits such as positive and rejuvenating transformers to prevent transformers from saturation. The design guide section introduces the calculations used in the design of the Fuscus pliers.

Power supply to IC AMP; UVL

IOU Lock Lock (UVL) comparator has two voltage reference values: start and stop threshold. During the power -on period, the UVL comparator disables VREF (Inturn disables the entire IC) until the controller reaches its VCC startup threshold. During the power off, the UVL comparator allows the controller to work until the VCC stops threshold. CS51221 only needs 50 micro -security during the startup process. In the lock mode, the output level remains in a low impedance state.

Under the conditions of power through power and failure, the soft start will hold the pinwing of the compressor pins and limit the duty cycle. Due to the low output voltage, the power -on conversion tends to generate a temporary duty cycle with much greater stability value. As a result, excessive current stress often occurs in the system. Soft startup technology eliminates the impact current by gradually release the duty duty clamping, thereby alleviating this problem. The duration of the soft start can be programmed by a capacitor connected to the SS pin. The constant charging current of the SS pin is 50 micro -security (typical values).

Typical performance features

VREF (OK) comparator monitor 3.3V VREF output. If VREF is lower than 3.1V, the fault state is locked. When the OV PIN voltage is higher than 2V or UV PIN voltage below 1V, the fault state may also be triggered. The underwriter comparator has a built -in lagging of 75MV (typical). OV comparator's magnetic stagnation can be programmed by the resistor connected to the OV pin. When the OV conditions are detected, the over -voltage lag current of 12.5μA (typical value) comes from the tube foot.

In Figure 4, the failure state is triggered by pulling the UV foot to the ground. Immediately, the SS capacitor is discharged at a current (typical value) of 5μA, and the gate output is disabled until the SS voltage reaches 0.3V discharge voltage (typical value valueTo. As shown in Figure 4, if the failure conditions are recovered, the IC starts the soft start conversion again. However, if the failure continues, the SS voltage will remain at 0.10V until the failure disappears.

current detection and overcurrent protection

The current can be monitored by the Isense tube foot to achieve pulse -by -limit flow. Various technologies can be used, such as current -fluctinated resistors or current transformers to export current signals. The voltage of the Iset pin sets the threshold of the maximum current. As shown in Figure 5, when the Isense Pin voltage exceeds the ISET voltage, the current limited comparator will reset the gate locking trigger to terminate the vein pulse.

The current detection signal is easy to generate cutting -edge peaks due to the switch conversion. The current signal is usually an RC low -pass filter to avoid premature triggers. However, low -pass filters will inevitably change the shape of the current pulse and increase costs. CS51221 uses a frontier anti -hidden circuit to block the front 150ns (typical value) of each current pulse. This can eliminate the front edge peak without changing the current waveform. During the soft start period and VCOMP, the faintness is disabled when the VCOMP is high, so that the minimum opening time of the controller does not have an additional hidden cycle. MAX SS DETECT comparator keeps disabled and disabled until SS is fully charged. When the output of the error amplifier reaches the saturated value, the output of the maximum duty cycle detection derivator becomes larger, indicating that the output voltage is far lower than its adjustment node, and the power supply may be in a load stress state.

oscillator and synchronization

The switching frequency can be programmed by the RC network connected to the RTCT pin. As shown in Figure 6, when the RTCT pin reaches 2V, the capacitor is discharged by a 1MA current source, and the door signal is disabled. When the RTCT tube foot is reduced to 1V, the gate output is connected, the discharge current is eliminated, and the RTCT tube foot rises. This will start a new switching cycle. The CT charging time is set up to the maximum duty ratio of the CT charging time, which can be programmed by the RT value shown in the design guide. At the beginning of each switching cycle, the synchronous pipe foot generates a pulse of 2.5V, 320ns (typical values). This pulse can be used to synchronize other power supply.

The two -way synchronization foot can also receive higher frequency external synchronous signals. As shown in Figure 7, when the synchronous pipe foot is triggered by the input signal, the IC discharge CT immediately. Once the RTCT pin reaches the valley voltage, the door signal is opened. Due to the steep decline, this valley voltage dropped below the normal 1V threshold. However, the RTCT pin voltage was subsequently increased by a clamp. When the RTCT pin reaches 0.95V (typical) valley voltage, the brief delay is cut off after a long delay, and the CT is charged through the RT.

The frequency and maximum duty occupation ratio of the switch

The time -time capacitor CT is charged by VREF through the VREF and discharged from the internal current source. During the discharge time, the internal clock signal sets the gate output to a low state, thereby providing the maximum duty cycle that can be selected by the user. The charging and discharge time is determined by the general formula;

In the formula: TC charging time; TD discharge time; vvalley valley voltage of the oscillator; vpeak oscillator of the oscillator Peak voltage.

Use typical values to replace the parameters in the above formulas:

vREF 3.3V, vvalley 1V, vpeak 2V, ID 1MA

It can be seen from the equation that the RT must be greater than 2.3K to work normally.

Select RC as a feeder slope

If the line voltage is far greater than the peak voltage of the FF pin, the charging current can be regarded as a constant, which is equivalent to vehicle identification Number/identification number. Therefore, the volume of the volt seconds is determined by the following formulas:

In the formula: vcomp compressor pin voltage, VFF (d) FF pin discharge voltage.

As shown in the equation, the voltage secondary clamp is set by the VCOMP clamp voltage setting equal to 1.8V. In positive or reverse circuits, the voltage secondary clamp value design is used to prevent transformers from saturation. In the Buck or FORWARD converter, the second second is equal to:

n transformer number ratio ratio

It is a constant, which is regulated output voltage, switching and switching The number of cycles and transformer turns ratio (BUCK converter uses 1). Interestingly, it can be noted from the above two equations that VCOMP will not change due to changes in the input voltage during steady state. This intuitively explains the reasons why the FF voltage mode control has superior line adjustment and line temporary response. Knowing the nominal values of vehicle recognition numbers (VIN) and Ton (TON), you can also choose the value of RC and place VCOMP in the center of its dynamic range.

Select the feedback pressure division

As shown in Figure 10, the pressure of the pressure device is fed in the FB pin, and the FB pin is connected to the reverse input of the error amplifier. The non -counter -phase input of the error amplifier is connected to 1.27V (typical) reference voltage. The FB tube foot has input current, and the current must be considered to achieve accurate DC output. The following formulas can be used to calculate the R1 and R2 values:

Mid -type #8711; is a correction coefficient caused by the existence of the FB pin input current IER.

RI FB pin and pressure divisionerDC resistance between output.

IER VFB input current, the typical value is 1.3 Weire.

Division device design for OV and UV detection

In FIG. 11See OV and UV thresholds.The resistance value can be calculated by the following three equations, and the third equation is derived from the requirements of OV lag.

In the formula: VLINE (low), VLINE (high) input voltage OV and UV threshold, VHYST vehicle identification number seen at the vehicle recognition number lags behind.

It is self -evident from Formula A and B. To use this design, the vehicle recognition number (high) must be twice as large as the vehicle identification number (low).Otherwise, two sorters must be used to program OV and UV separately.

Surface installation of narrow body (d); 150 mil width