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2022-09-15 14:32:14
L6713A for 2/3 phase controllers and AMD6 -bit CPUs for Intel VR10 and VR11 with embedded drivers (1)
General features
Load transient boost (LTB) technology #8482; to minimize the number of output capacitors as much as possible (is applying for a patent)
123] Optional 2 or 3 phase operations
0.5%output voltage accuracy
7/8-bit programmable output of 1.60000V -Intel VR10.x, VR11 DAC
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123] 6-bit programmable output of 1.5500V-AMD 6-bit DACLarge-current integrated door drive
Through the full difference in the influenza in the sensor
Embedded VRD Thermal monitoring vision
Differential remote sensing voltage
Dynamic video management
adjustable voltage shift
Low -side start
programming soft soft Start
Programmable overvoltage protection
Preliminary overvoltage protection
Aerable current protection
Avable switching frequency
Output output Enable
SS_END/PGOOD signal
tqfp64 10x10mm packaging, with an externally exposed pad
The large -current VRD of desktop CPU
Workstation and server CPU power supply
VRM module
Instructions
L6713A execute two/three -phase lower voltage reduction controllers with 180o/120o phase shifts each phase integrated high -current drive compact Type 10x10mm body component cushion. That 2 or 3 phase operations are easy to choose pins through phase. Load transient voltage (LTB) technology #8482; (patent to be set) By providing, the fastest response to load conversion requires less volume and ceramic output capacitance to meet the load transient requirements. LTB technology #8482; It can be disabled and the conditions of this conditional device are used as a bilateral work asynchronous PWM. Device embedded in the selected DAC: the output voltage range is as high as 1.60000V (both Intel VR10.X and VR11 DAC) or up to 1.5500V (AMD 6-digit DAC) with ± 0.5%output voltage to manage D-VID lines and temperature changes with temperature changes. Accuracy. The controller ensures that the fast protective load is over -current and the under pressure/overvoltage is also before UVLO). When the device is over, the device shuts down all MOSFETs and locks the conditions. A system heating monitor is also provided to allow the system to overheat protection conditions.
Electric characteristics
VCC u003d 12V ± 15%, TJ u003d 0 ° C to 70 ° C, unless there are other regulations
Device description
L6713A It is a dual/three-phase PWM controller, a built-in large current driver, which provides a complete control logic of high-performance antihypertensive DC-DC voltage and protecting the regulator to optimize the advanced microprocessor power supply. Multi -phase buck is the simplest and most economical topology, which can meet the demand for new microprocessors and modern large -current VRMs to continuously increase modules. It allows smaller, cheaper and the most common external power MOSFET and inductors. Moreover, thanks to each phase of each phase, the results of the input and output capacitors are reduced. Phase interlacing actually leads to a decrease in the input average root current and output ripple voltage and showing an effective output switch frequency: the free operation frequency of 200kHz per phase can be adjusted by the resistor through the resistor. Essence L6713A is a bilateral asynchronous PWM controller with a load transient pressure (LTB) technology #8482; (being applying for a patent): This device will be opened at the same time Quick response to load conversion. Detecting load conversion (through LTB pins) measured the guide number DV/DT voltage and DV/DT that can be easily programmed and expanded the flexibility of the system design. In addition, the load transient boost (LTB) technology #8482; gain can be easily modified to control the output voltage back ring. LTB technology #8482; can be disabled. In this case, the device is an asynchronous PWM as a bilateral work. The controller allows the implementation of scalable design: Three -phase design can easily achieve only one phase without installation and leave to downgrade the two phases to choose the pin. The same design can be used for multiple items to save development and debugging. Similarly, the two -stage design can be further upgraded to the three -phase application of updates and high requirements. L6713A allows the current reading through the sensor to complete the number of currents, thereby simplifying the system design differential mode. You can also consider the sensing resistance connected to the inductor to improve the reading accuracy. Reading current information correction PWM output so that the average value is equal to under static and dynamic conditions, and the current loaded currently limits the error at ± 3%unless the expansion of the sensor element is taken into account. The controller includes multiple DACs, which can be selected by appropriate pins to allow the D-VID conversion to be compatible with Intel VR10, VR11, and AMD 6bit processor specifications at the same time. The low -side startup allows soft startup to exceed the premium output to avoid the risk of dangerous currents passing through the main electromoter and the negative peak of the load side.
L6713A provides a programmable overvoltage protection to protect excessive pressure on load danger. It can be set to a fixed voltage resistance by appropriate external settings, or can be set inside, by opening the lower drive andDrive high fault pins. In addition, preliminary OVP protection also allows device protection load VCC to be dangerous OVP when it is not higher than the UVLO threshold. Excessive current protection acts on the total output current and causes the device to turn to turn off all MOSFET and lock the status. L6713A also provides systematic thermal monitoring: The temperature result of the hottest component in the application of an appropriate pins device sensing warning is alarm signal. Compact 10 x 10 mm fuselage TQFP64 packaging, with exposed heat sink pads, can heat the power supply of external MOSFET through the system board.
Configuration Device
Before the system starts, the number of pins and ss/LTBG/AMD pins with appropriate pins and SS/LTBG/AMD pins of multiple DAC programming needs to be configured. The configuration of this pin determines the difference between the two main work areas (see Table 11) in line with Intel VR10, VR11 or AMD 6bit specifications. According to the main norms, further customization can be carried out: the main difference is about DAC tables, soft startup implementation, protecting management and dynamic video conversion. For more detailed information about the equipment, see Table 12 and 13 configurations.
Phase Selection 
DAC selection 
]
Note: When selecting the Intel mode, the SS/LTBG/AMD pin is used to choose a soft start time and long -term borrowing #8482; gain (see the dedicated part) output voltage through VID pins programming: they are what they are The input of the internal DAC is a reference to achieve the resistance of the internal voltage partition through a series of resistance. VID code drives the multi -road relics, in the separation line. DAC output is transmitted to the amplifier that obtains the reference voltage (that is, the setting value of the error amplifier, VREF).
Power loss
L6713A is high and low -side MOSFET embedded in high -current MOSFET drives: IT and then consider the power consumed by the device when driving them. It is very important to avoid overcoming the highest work temperature. In addition, because the device has a naked pad to better dissipate power, the layout between the heat resistance connection and the surrounding environment is also important: heat dissipation padsYou need to welded through several pores to the PCB ground layer to dissipate heat. Two aspects: driver power and driving power. The first (PDC) depends on the static consumption of the device through the static consumption of the power pins. ] 
Among them, n is the number. The driver's power supply is the driver's continuous opening and turning off the external MOSFET; it is the function of the switch frequency and the function of the total grid charge. There are three main factors that consider the total power PSW to dissipate to the switch MOSFET (easy calculation): the outer grid pole resistance (if existence), the MOSFET resistor, and the drive resistor resistance. This last item is an important item that needs to be determined in the power consumption calculation of the device. The total power result consumed by the switch MOSFET:
The external gate resistance helps the device to dissipate the switch power Share sharing leads to the general cooling of the device. When connecting multiple MOSFETs in parallel, it is recommended to use a gate resistor per MOSFET.
The current reading and the balance circuit
l6713A embedded in a flexible, full differential current detection circuit, which can read the parasitic resistance of the power sensor or connected in series in series Sensor on the sensor. Components that can inhibit the noise and allow the placement of sensing accuracy without the measurement accuracy. When reading the current passing through the inductor DCR, the current is transformed into a current to the current when the current is read through the voltage drop when the output induction or sensor or the sensing resistance string is connected to the current. The anti -missile ratio is placed between the outer CSX pin from the outer resistance RG, facing the reading point. The current detection circuit always tracks the current information, and does not generate the bias current from the CSX+pin: This pins are used as a reference to keep the CSX pin voltage. To correctly reproduce the inductance current, the R-C filter network must be parallel to the sensing element. The current flowing out from the CSX pin is given by the following formula (see Figure 8):
Now consider the time constant of the matching of the electrical and the R-C filter (time constant constant Do not match the introduction of electrodes in the current read number network to cause unstable. In addition, the load transient response is also very important to display the resistance equivalent output impedance), result:
Among them Iinfo is the current information of internal replication.
The following formulas must be used in order to select the RG anti -electrical resistor to ensure the correct function of the internal current reading circuit: 
The average current reported in FIG. 9 Control loop: It believes that current IINFOX and each phase current and average current. Error reading current iinfox andThe voltage between IAVG is converted to the use of appropriate gains to adjust the duty occupation ratio. Their dominant value is placed by the voltage error to balance the current carried by each phase. As shown in Figure 8.
Differential remote sensing voltage
detect the output voltage under the full differential mode between FB and FBG pins. The FB pin must be connected to the regulatory node through the resistor, and the fiber grating pin must be directly connected to the remote sensing location. In this way, the programming output voltage is adjusted between the remote sensing point to adjust the compensation motherboard or connector loss. Keep the FB and FBG trajectories parallel and be protected by the power board. As a result, it is a common mode coupling of any picker noise. 
The output voltage positioning is selected to the reference value by selecting the benchmark DAC and programming speed drop function and offset (see Figure 11). The VSEN pins that are sagging and sinking cause the output voltage according to the external RFB and ROFFSET resistors. The output voltage is driven by the following relationship:
Can disable the speed reduction and speed reduction connection function
Solding together to achieve the dependence of load adjustment, and If this effect is not satisfactory, by short circuit to SGND, the device can be used as a classic voltage running mode reduction converter. Speed u200bu200bsales can also be connected to SGND to obtain a voltage that is proportional to the current that can be monitored. Using ROFFSET is equal to zero to disable offset.
Partial displacement (optional)
iOFFSET current from VSEN pin (see Table 4) allows programming to be through VSEN pins and pins and VOUT, as shown in Figure 11; in addition to this offset, it is necessary to consider that the offset is already introduced in the production stage and the VR11 mode is introduced. The output voltage programming is as follows:
DAC selects the automatic offset given by DAC differently
compensation current: The built -in characteristics are in production. Make fine -tuning to ensure that the error (AMD DAC is ± 0.6%) of ± 0.5%is overload and line changes.
Speed u200bu200breduction function (optional)
This method ""recovery"" section due to the decreased transient caused by the output capacitance ESR in the load, the dependence of the output voltage to the load current: Static static The proportion of errors to the output current causes the output voltage according to the current. As shown in Figure 11, the decrease in ESR exists in any case, but the total deviation of the total output voltage of the speed reduction function is minimized. And more and more high -performance CPUs require precise load -end adjustment to work normally. The speed reduction function not only needs to optimize the output filter, but also needsTo load requirements. Connect the sagging pipe foot and FB pin together. The device will forced the current IDROOP to be proportional to the reading current, and enter the feedback resistor (RFB+ROFFSET) to achieve load adjustment dependence. Because IDROOP relies on N's current information phase, the relationship between the output characteristics and load current (ignore the offset voltage item): 
(Or induction resistance during use), iOUT is the system output current. The entire power supply can be used to represent the voltage generator with an equivalent output resistance RDROOP and voltage value VREF. The RFB resistor can also be designed as follows according to the RDROOP specification:
The speed drop function is optional. If it is not needed, it can be disconnected from FB. Information debugging and/or current monitoring of current. When not in use, the pins can be shortened to SGND
load transient boost technology
Load transient boost (LTB) technology #8482; (being applying for patent) is L6713A A function can consider the counting specifications of the output filter capacitor (MLCC and large capacitors) of the load transient. Once the load is detected, the device will be opened at the same time to keep them running within the necessary time for loading. This time depends on the compensation pin voltage and internal gain to maintain the response of the output voltage. DV/DT, which is connected to RLTB-CLTB and VOUT: LTB pin detection load conversion to measure the output voltage of the device, so it can be connected to all phase after the load transfer detection immediately, minimizing delay intervention. Modifying the RLTB-CLTB value DV/DT can be easily programmed and expanded the system design flexibility
