Features

ESD protection of high-speed data cable:

-Excess: IEC 61000-4-2 (ESD) ± 24kV (air), ± 24kV (contact point contacts )

-IEC 61000-4-5 (Lightning) 4A (8/20 microsecond)

-Human model (HBM) ± 24kV

Small Packaging saves board space

Low insertion loss

Protect four I/O lines

low clamp voltage

Low operating voltage: 5.0V

Application

USB 2.0 Power and Data Cable Protection

Video graphics card

display and tablet display

Digital video interface (DVI)

General description

aoz8904 [123 ] It is a transient voltage suppressor array, which is used to protect the effects of high -speed data cables from static discharge (ESD) and lightning.

Ordering information

pins configuration

[ 123]

Typical performance features

Application information AOZ8904 TV design The effect of quickly destroying the transient overvoltage is to fix it to a reference voltage. When the transients on the protected data cable exceed the reference voltage, the turning diode is the positive bias, so that the harmful ESD transient is far from the protected sensitive circuit.

Print circuit board layout guide

The layout of the printing circuit board is the key to achieving the highest level of resistance on the power line and data cable. The position of the protection device on the PCB isThe simplest and most important design rules. The AOZ8904 device should be as close to the noise source as possible. The location of the AOZ8904 device is applied to all data and power cords that enter or exit the PCB at the input/output connector. In most systems, the surge pulse occurs on the data and power line entered the PCB through the I/O connector. Place the AOZ8904 device as close to the noise source as much as possible to ensure that the wave voltage will be tied before the pulse coupling to the adjacent PCB recorder. In addition, the printing circuit board should use as short trajectories as possible. The length of the short record is equivalent to low impedance, which ensures that the surge energy will be dissipated by the AOZ8904 device. The long signal trajectory will act as an antenna, which receives energy generated from the static discharge pulse. Through the length of the line as short as possible, the efficiency of the line antenna related to the static discharge can be reduced. By placing the most connected devices at as possible as possible, the length of the interconnection is minimized. The protection circuit should be diverted to the reference or the chassis ground. Digging of the swarm voltage directly to the signal of the integrated circuit can cause ground rebound. By reducing the impedance of relatively short and wide grounding paths, the clamp performance of the TVS diode on a single ground PCB can be improved. The layout and integrated circuit packaging parasite of the printing circuit board will cause significant super adjustment to the clamp voltage of the TV. Using short trajectory length and multi -layer independent ground floor and power supply can reduce the inductance of PCB. One of the effective ways to minimize circuits is to include a ground plane in the PCB design. AOZ8904 Ultra -low -capacitor TV is designed to protect the four high -speed data transmission cables from being influenced by transient overvoltage. The method is to fix them on a fixed benchmark. Low inductors and structures make the voltage of large -current rice superilation. When the voltage on the protective line exceeds the reference voltage, the internal turning to the diode positive bias, causing the transient current to away from the sensitive circuit.

A good circuit board layout is essential for the transient change caused by electrostatic discharge. It is recommended to follow the following criteria:

1. Place the TV near the IO terminal or connector to limit the transient coupling.

2. Fill the unused part of the PCB plane.

3. The length of the path between the TV and the protected line.

4. minimize all conductive circuits, including power supply and grounding circuit.

5. ESD transient grounding circuit should be as short as possible.

6. Do not run key signals near the edge of the circuit board.

7. Use the ground plane as much as possible.

8. Avoid running key signal trajectories (clocks, reset, etc.) near the edge of PCB.

9. Separate the chassis traces with components and signal marks at least 4 mm.

10. Keep the chassis ground -width ratio lt; 5: 1, minimize the inductance.

11.Protect all external connections with TV diode.

1 The size of the bag does not include mold flying edges and mouthbrids. The non -lead -side mold flash should be less than 5 mils. 2. The size L " measured in the instrument plane.

3. ± 0.100 mm (4 mil)